Yeonwoo Ku

Joonhee Lee

Jaewook Kim

Junghyup Lee

Dongmin Park

Jaewon Lee

Pyoungwon Park

Kwangseok Kim

Woojae Lee

Wonsik Yu

Younghwa Kim

Youngwoo Jo

Hyojun Kim

Dongin Kim

Yongjo Kim

Seongseop Lee

Nahmil Koo

Myungjun Kim

Sujin Park

Hyunsik Jeong

Jin-O Seo

DongArm Shin

Han Gil Choi

Hyuk Jin Lee

Somyung Ha

Taekwang Jang

Sungjun Kim

Younggyu Yoon

Sehyung Jeon

Wookon Son

Minchang Cho

Sungjin Kim

Jaehyun Han

Sungpah Lee

Kangyeop Choo

Hyoungtaek Choi

Jinwoo Sang

Jungho Kim

Gyusik Kim

Zilong Han

Minyoung Kang

John Kang

SungRok Jeon

Hyunik Kim

Seonggyu Lee

Jinsoo Choi

Jonghwa Lee

Jusung Lee

GeonHwi Lee

Jinseok Lee

Jihwan Kim

Dohun Jang

Dong Hee Kim

Dongkyun Jung

Yeonwook Jung

Kyunghyun Kim

JunSeok Hong

Yubin Kim

Hyein Yoon

Youngjae Son

Kiwon Lee

Sihoon Yang

Our group's research focus is on the design of analog integrated circuits with multiple layers of system abstraction in mind, from algorithms and system architectures to circuit techniques. Our main area of research is 1) high-speed circuits for wireline & wireless communication 2) low-power circuits for sensor applications including battery management and biomedicine 3) machine learning and memory circuits.

연구실은 통신, 바이오 응용 및 신기술을 위한 아날로그 및 혼합 신호 집적 회로 설계에 중점을 둡니다.

A 43 nW, 32 kHz, ±4.2 ppm Piecewise Linear Temperature-Compensated Crystal Oscillator With ΔΣ-Modulated Load Capacitance

Adaptive Clocking Using Supply Tracking Clock Modulator With Background-Calibrated Supply Sensitivity

A Single BJT Bandgap Reference with Frequency Compensation Exploiting Mirror Pole

A 24.8
W Biopotential Amplifier Tolerant to 15-VPP Common-Mode Interference for Two-Electrode ECG Recording in 180nm CMOS

A 0.0082-mm², 192-nW Single BJT Branch Bandgap Reference in 0.18-μm CMOS

A sleep apnea monitoring IC for respiration, heart-rate, SpO2 and pulse-transit time measurement using thermistor, PPG and bodychannel communication

A 2.92-μW Capacitance-to-Digital Converter With Differential Bondwire Accelerometer, On-Chip Air Pressure, and Humidity Sensor in 0.18-μm CMOS

An On-Chip Thermal Monitoring System with a Temperature Sensing Area of 52 µm2 in 180nm CMOS

A Second-Order ΔΣ Time-to-Digital Converter Using Highly Digital Time-Domain Arithmetic Circuits

A Hybrid PLL Using Low-Power GRO-TDC for Reduced In-Band Phase Noise

A Low-power Photoplethysmogram-based Heart Rate Sensor using Heart Beat Locked Loop

A 3.2GHz Supply Noise Insensitive PLL using a Gate Voltage boosted Source-Follower Regulator and Residual Noise Cancellation

An Ultra-high Input Impedance Analog Front-end with Self-calibrated Positive Feedback

A 2.4-GHz 1.5-mW Digital Multiplying Delay-Locked Loop Using Pulsewidth Comparator and Double Injection Technique

A Relative Permittivity-Based Air Pressure Sensor Using Standard CMOS Process

A 2.3mW, 0.01mm2, 1.25GHz Quadrature Signal Corrector with 1.1ps error for Mobile DRAM Interface in 65nm CMOS

A 1-GS/s 9-bit Zero-Crossing-Based Pipeline ADC Using a Resistor as a Current Source

A 0.22 psrms Integrated Noise 15 MHz Bandwidth Fourth-Order ΔΣ Time-to-Digital Converter Using Time-Domain Error-Feedback Filter

A Hybrid-domain Two-step Time-to-Digital converter Using Switch-Based Time-to-Voltage converter and SAR ADC

Integrated All Electrical Pulse Wave Velocity & Respiration Sensors using Bio-impedance

A 148fsrms Integrated Noise 4MHz Bandwidth Second-Order Delta-Sigma  Time-to-Digital Converter With Gated Switched-Ring Oscillator

A 9b, 1.12ps resolution 2.5 b/Stage Pipelined Time-to-Digital Converter in 65nm CMOS Using Time-Register

A 7b, 3.75ps resolution two-step time-to-digital converter in 65nm CMOS using pulse-train time amplifier

A Time-Domain High-Order MASH Delta-Sigma ADC using Voltage-Controlled Gated-Ring Oscillator

A 14.2 mW 2.55-to-3 GHz cascaded PLL with reference injection and 800MHz ΔΣ modulator in 0.13μm CMOS

A Digital-Intensive MMMB Receiver Using a Sinc2 filter-Embedded VCO-Based ADC

A 2.4GHz Fractional-N Frequency Synthesizer with High-OSR DS Modulator and Nested PLL

A 1.4 µW 24.9 ppm/◦C current reference with process insensitive temperature compensation in 0.18 µm CMOS

A high-frequency compensated crosstalk and ISI equalizer for multi-channel on-chip interconnect in 130-nm CMOS

A Highly-Digital VCO-based Analog-to-Digital Converter using Phase Interpolator and Digital Calibration

A 2.5-Gb/s on-chip interconnect transceiver with crosstalk and ISI equalizer in 130 nm CMOS

A 470-uW 5-GHz Digitally Controlled Injection-Locked Multi-Modulus Frequency Divider with
an In-Phase Dual-Input Injection Scheme

A Low-Noise and Low-Power Frequency Synthesizer Using Oﬀset Phase-Locked Loop in 0.13um CMOS

Analysis and Design of Voltage-Controlled Oscillator-Based Analog-to-Digital Converter

Nth-order multi-bit delta-sigma ADC using SAR quantiser

An Ultra Low Power and Variation Tolerant GEN2 RFID Tag Front-End with Novel Clock-Free Decoder

Design Techniques for a Low-Voltage VCO with Wide Tuning Range and Low Sensitivity to PVT Variations

A 1.8 V 900-µW 4.5 GHz VCO and Prescaler in 0.18µm CMOS Using Charge-Recycling Technique

A Low-Jitter Area-Eﬃcient LC-VCO Based Clock Generator in 0.13 um CMOS

A Time-based Bandpass ADC using Time-Interleaved Voltage-Controlled Oscillators

A Self Noise Canceling Technique for Voltage-Controlled Oscillators

Digitally Controlled Oscillator with High Frequency Resolution using Novel Varactor Bank

An Optimum Current Mirror Ratio for Low Phase Noise LC-VCO

A Quadrature Modulation Transmitter Using Two Frequency Synthesizers

Highly Linear and Low Noise 2.4-GHz RF Front-End Circuits Using Transformer and Vertical NPN BJT

Close-in Phase-Noise Enhanced Voltage-Controlled Oscillator Employing Parasitic V-NPN Transistor in CMOS Process

Design Considerations for Ultra-low Energy Wireless Microsensor Nodes

A 6.5GHz Energy-efficient BFSK modulator for wireless sensor applications

Design considerations for energy-eﬃcient radios in wireless microsensor networks

A Behavioral Modeling Approach to the Design of a Low Jitter Clock Source

Energy-centric enabling technologies for wireless sensor networks

Design of Low Power Variable Length Decoder Using Fine Grain Non-Uniform Table Partitioning

A Fast-Settling mm-Wave LO With I/Q-Calibrated SSB Mixer and Frequency-Tuned ILO Filter Achieving Sub-ns Settling Time and -56 dBc Spur

Energy-Efficient Data Transmitters Achieving Energy Per Bit Beyond CV2 Limitation

A Fully Integrated 4:1 DC–DC Converter With Series Transmission and Parallel Reception Through Electromagnetically Coupled Class-D LC Oscillators

A 7.5GHz Subharmonic Injection-Locked Clock Multiplier Featuring a 120x Multiplying Factor and 92.3fs RMS Jitter Including Reference Spur

A PVT-Insensitive Sub-ranging Current Reference Achieving 11.4-ppm/°C from −20 °C to 125 °C

A 0.001-mm2, 1.15-11 GHz Background Quadrature Phase and Duty-Cycle Error Corrector Using a NAND-based Phase Detector in 28-nm CMOS

A Jitter Programmable Digital Bang-Bang PLL Using PVT-Invariant Stochastic Jitter Monitor

A 44.2-TOPS/W CNN Process With Variation-Tolerant Analog Datapath and Variation Compensating Circuit

An Adaptive Filter Based Motion Artifact Cancellation Technique Using Multi-wavelength PPG for Accurate HR Estimation

An Output-Capacitorless Analog LDO Featuring Frequency Compensation of Four-Stage Amplifier

A 3.68a F rms Resolution Continuous-Time Bandpass ΔΣ Capacitance-to-Digital Converter for Full-CMOS Sensors in 0.18 μm CMOS

A Supply Noise Induced Jitter Canceling Adaptive Filter for LPDDR5 Mobile DRAM

43.3µW Biopotential Amplifier with Tolerance to Common-Mode Interference of 18Vpp and T-CMRR of 105dB in 180nm CMOS

A 43 nW, 32 kHz, A 43 nW, 32 kHz, ±4.2 ppm Piecewise Linear Temperature-Compensated Crystal Oscillator With ΔΣ-Modulated Load Capacitance

A 24.8µW Biopotential Amplifier Tolerant to 15-VPP Common-Mode Interference for Two-Electrode ECG Recording in 180nm CMOS

A 0.0082-mm², 192-nW Single BJT Branch Bandgap Reference in 0.18-µm CMOS

A 2.92-µW Capacitance-to-Digital Converter With Differential Bondwire Accelerometer, On-Chip Air Pressure, and Humidity Sensor in 0.18-μm CMOS

Physical layer driven protocol and algorithm design for energy-efficient wireless sensor networks

Low-power wireless sensor networks

Design considerations for distributed microsensor systems

Analysis and design of voltage-controlled oscillator based analog-to-digital converter

Design considerations for ultra-low energy wireless microsensor nodes

Self-powered wearable electrocardiography using a wearable thermoelectric power generator

Energy efficient modulation and MAC for asymmetric RF microsensor systems

A 9 bit, 1.12 ps resolution 2.5 b/stage pipelined time-to-digital converter in 65 nm CMOS using time-register

An architecture for a power-aware distributed microsensor node

Power aware wireless microsensor systems

A time-based analog-to-digital converter using a multi-phase voltage controlled oscillator

Energy-efficient link layer for wireless microsensor networks

Design considerations for energy-efficient radios in wireless microsensor networks

A 1.4-µW 24.9-ppm/° C current reference with process-insensitive temperature compensation in 0.18-µm CMOS

Energy efficient protocols for low duty cycle wireless microsensor networks

A 95nW ring oscillator-based temperature sensor for RFID tags in 0.13 µm CMOS

A 10MHz 80μW 67 ppm/° C CMOS reference clock oscillator with a temperature compensated feedback loop in 0.18 μm CMOS

Rex Min, Amit Sinha, Alice Wang, and Anantha Chandrakasan. Physical layer driven protocol and algorithm design for energy-efficient wireless sensor networks

Cho's Circuits & Systems Lab

교수님 소개

한전석좌교수

연구실 소개

연구실 키워드

알럼나이가 간 회사

연구실 지원 방법

대우 조건

연도별 논문 인용수

저널 & 학회 논문 출판 수

연구실 논문 목록

A 7.5GHz Subharmonic Injection-Locked Clock Multiplier Featuring a 120x Multiplying Factor and 92.3fs RMS Jitter Including Reference Spur

A PVT-Insensitive Sub-ranging Current Reference Achieving 11.4-ppm/°C from −20 °C to 125 °C

A 0.001-mm2, 1.15-11 GHz Background Quadrature Phase and Duty-Cycle Error Corrector Using a NAND-based Phase Detector in 28-nm CMOS

연구실 보유 특허

대학별 입시끈

우리 연구실 모집

교수님 소개

한전석좌교수

연구실 키워드

알럼나이가 간 회사

연구실 지원 방법

대우 조건

연도별 논문 인용수

저널 & 학회 논문 출판 수

연구실 논문 목록

A 7.5GHz Subharmonic Injection-Locked Clock Multiplier Featuring a 120x Multiplying Factor and 92.3fs RMS Jitter Including Reference Spur

A PVT-Insensitive Sub-ranging Current Reference Achieving 11.4-ppm/°C from −20 °C to 125 °C

A 0.001-mm2, 1.15-11 GHz Background Quadrature Phase and Duty-Cycle Error Corrector Using a NAND-based Phase Detector in 28-nm CMOS

연구실 보유 특허

최근 3년간 연구실적 높은 연구실

대학별 입시끈

우리 연구실 모집