Youngeun Kwon

Yujeong Choi

Bongjoon Hyun

Ranggi Hwang

Yunjae Lee

Taehun Kim

Yunseong Kim

Minhoo Kang

Dongho Yoon

Beomsik Park

Jehyeon Bang

Yoonhyuk Choi

Jiin Kim

Gwangoo Yeo

Dongjae Lee

Juntaek Lim

Eunyeong Cho

Hyeseong Kim

Seongjin Gong

Hyesung Ahn

The Vertically Integrated Architecture (VIA) research group, associated with KAIST's School of Electrical Engineering, Department of Semiconductor System Engineering, Graduate School of AI, and Graduate School of AI Semiconductor, conducts computer architecture research. It employs a vertically integrated approach, co-optimizing VLSI technology, computer system architecture, and applications & algorithms, to develop high-performance computing platforms for programmable, robust, reliable, secure, and energy-efficient intelligent systems.

KAIST 전기공학부, 반도체시스템공학과, 인공지능대학원, AI반도체대학원에 소속된 VIA (Vertically Integrated Architecture) 연구 그룹은 컴퓨터 구조 연구를 수행한다. VLSI 기술, 컴퓨터 시스템 구조, 애플리케이션 및 알고리즘을 공동으로 최적화하여 프로그래밍 가능하고 견고하며 안정적이고 안전하며 에너지 효율적인 지능형 시스템을 위한 고성능 컴퓨팅 플랫폼 개발에 중점을 둔다.

Exploring KV Cache Quantization in Multimodal Large Language Model Inference

PIM-malloc: A Fast and Scalable Dynamic Memory Allocator for Processing-In-Memory (PIM) Architectures

PASCAL: A Phase-Aware Scheduling Algorithm for Serving Reasoning-based Large Language Models

The Cost of Dynamic Reasoning: Demystifying AI Agents and Test-Time Scaling from an AI Infrastructure Perspective

Hera: A Heterogeneity-Aware Multi-Tenant Inference Server for Personalized Recommendations

Mamba-X: An End-to-End Vision Mamba Accelerator for Edge Computing Devices

Debunking the CUDA Myth Towards GPU-based AI Systems

A Characterization of Generative Recommendation Models: Study of Hierarchical Sequential Transduction Unit

Characterization and Analysis of the 3D Gaussian Splatting Rendering Pipeline

Characterization and Analysis of Text-to-Image Diffusion Models

Uncovering Real GPU NoC Characteristics: Implications on Interconnect Architecture

PIM-MMU: A Memory Management Unit for Accelerating Data Transfers in Commercial PIM Systems

vTrain: A Simulation Framework for Evaluating Cost-effective and Compute-optimal Large Language Model Training

A Quantitative Analysis of State Space Model-based Large Language Model: Study of Hungry Hungry Hippos

Analysis of Data Transfer Bottlenecks in Commercial PIM Systems: A Study with UPMEM-PIM

Pre-gated MoE: An Algorithm-System Co-Design for Fast and Scalable Mixture-of-Expert Inference

PreSto: An In-Storage Data Preprocessing System for Training Recommendation Models

ElasticRec: A Microservice-based Model Serving Architecture Enabling Elastic Resource Scaling for Recommendation Models

La zyDP: Co-Designing Algorithm-Software for Scalable Training of Differentially Private Recommendation Models

GPU-based Private Information Retrieval for On-Device Machine Learning Inference

Pathfinding Future PIM Architectures by Demystifying a Commercial PIM Technology

FPGA-Accelerated Data Preprocessing for Personalized Recommendation Systems

GROW: A Row-Stationary Sparse-Dense GEMM Accelerator for Memory-Efficient Graph Convolutional Neural Networks

HAMMER: Hardware-friendly Approximate Computing for Self-attention with Mean-redistribution and Linearization

DiVa: An Accelerator for Differentially Private Machine Learning

ARK: Fully Homomorphic Encryption Accelerator with Runtime Data Generation and Inter-Operation Key Reuse

PARIS and ELSA: An Elastic Scheduling Algorithm for Reconfigurable Multi-GPU Inference Servers

SmartSAGE: Training Large-scale Graph Neural Networks using In-Storage Processing Architectures

Training Personalized Recommendation Systems from (GPU) Scratch: Look Forward not Backwards

BTS: An Accelerator for Bootstrappable Fully Homomorphic Encryption

TRiM: Enhancing Processor-Memory Interfaces with Scalable Tensor Reduction in Memory

Characterization and Analysis of Deep Learning for 3D Point Cloud Analytics

Understanding the Implication of Non-Volatile Memory for Large-Scale Graph Neural Network Training

Tensor Casting: Co-Designing Algorithm-Architecture for Personalized Recommendation Training

LazyBatching: An SLA-aware Batching System for Cloud Machine Learning Inference

Trident: A Hybrid Correlation-Collision GPU Cache Timing Attack for AES Key Recovery

TRiM: Tensor Reduction in Memory

Centaur: A Chiplet-based, Hybrid Sparse-Dense Accelerator for Personalized Recommendations

NeuMMU: Architectural Support for Efficient Address Translations in NPUs

PREMA: A Predictive Multi-task Scheduling Algorithm For Preemptible Neural Processing Units

TensorDIMM: A Practical Near-Memory Processing Architecture for Embeddings and Tensor Operations in Deep Learning

A Disaggregated Memory System for Deep Learning

Beyond the Memory Wall: A Case for Memory-centric HPC System for Deep Learning

A Case for Memory-Centric HPC System Architecture for Training Deep Neural Networks

Compressing DMA Engine: Leveraging Activation Sparsity for Training Deep Neural Networks

Accelerator-centric Deep Learning Systems for Enhanced Scalability, Energy-Efficiency, and Programmability

GPUpd: A Fast and Scalable Multi-GPU Architecture Using Cooperative Projection and Distribution

SCNN: An Accelerator for Compressed-sparse Convolutional Neural Networks

Architecting an Energy-Efficient DRAM System For GPUs

vDNN: Virtualized Deep Neural Networks for Scalable, Memory-Efficient Neural Network Design

CLEAN-ECC: High Reliability ECC for Adaptive Granularity Memory System

Priority-Based Cache Allocation for Throughput Processors

GPUVolt: Characterizing and Mitigating Voltage Noise in GPUs

A Locality-Aware Memory Hierarchy for Energy-Efficient GPU Architectures

Maximizing SIMD Resource Utilization in GPGPUs with SIMD Lane Permutation

The Dual-Path Execution Model for Efficient GPU Control Flow

CAPRI: Prediction of Compaction-Adequacy for Handling Control-Divergence in GPGPU Architectures

Optimization of Arithmetic Coding for JPEG2000

Memory-less Bit-Plane Coder Architecture for JPEG2000 with Concurrent Column-Stripe Coding

Architecture Design of a High-Performance Dual-Symbol Binary Arithmetic Coder for JPEG2000

A Novel Trace-Pipelined Binary Arithmetic Coder Architecture for JPEG2000

SCNN: An accelerator for compressed-sparse convolutional neural networks

vDNN: Virtualized deep neural networks for scalable, memory-efficient neural network design

Tensordimm: A practical near-memory processing architecture for embeddings and tensor operations in deep learning

Compressing DMA engine: Leveraging activation sparsity for training deep neural networks

Bts: An accelerator for bootstrappable fully homomorphic encryption

Prema: A predictive multi-task scheduling algorithm for preemptible neural processing units

A locality-aware memory hierarchy for energy-efficient GPU architectures

Ark: Fully homomorphic encryption accelerator with runtime data generation and inter-operation key reuse

Centaur: A chiplet-based, hybrid sparse-dense accelerator for personalized recommendations

Architecting an energy-efficient dram system for gpus

Priority-based cache allocation in throughput processors

Beyond the memory wall: A case for memory-centric hpc system for deep learning

The dual-path execution model for efficient GPU control flow

Lazy batching: An SLA-aware batching system for cloud machine learning inference

TRiM: Enhancing processor-memory interfaces with scalable tensor reduction in memory

CAPRI: Prediction of compaction-adequacy for handling control-divergence in GPGPU architectures

Maximizing SIMD resource utilization in GPGPUs with SIMD lane permutation

Smartsage: training large-scale graph neural networks using in-storage processing architectures

Tensor casting: Co-designing algorithm-architecture for personalized recommendation training

Grow: A row-stationary sparse-dense gemm accelerator for memory-efficient graph convolutional neural networks

VIA Research Group

교수님 소개

민수루

연구실 소개

연구실 키워드

알럼나이가 간 회사

연구실 지원 방법

대우 조건

연도별 논문 인용수

저널 & 학회 논문 출판 수

연구실 논문 목록

Exploring KV Cache Quantization in Multimodal Large Language Model Inference

PIM-malloc: A Fast and Scalable Dynamic Memory Allocator for Processing-In-Memory (PIM) Architectures

PASCAL: A Phase-Aware Scheduling Algorithm for Serving Reasoning-based Large Language Models

연구실 보유 특허

대학별 입시끈

우리 연구실 모집

교수님 소개

민수루

연구실 키워드

알럼나이가 간 회사

연구실 지원 방법

대우 조건

연도별 논문 인용수

저널 & 학회 논문 출판 수

연구실 논문 목록

Exploring KV Cache Quantization in Multimodal Large Language Model Inference

PIM-malloc: A Fast and Scalable Dynamic Memory Allocator for Processing-In-Memory (PIM) Architectures

PASCAL: A Phase-Aware Scheduling Algorithm for Serving Reasoning-based Large Language Models

연구실 보유 특허

최근 3년간 연구실적 높은 연구실

대학별 입시끈

우리 연구실 모집