Son Dongjun (손동준)

Chung Keun-Yong (정근용)

Kim MinCheol (김민철)

Heo Gyeongchan (허경찬)

Kim Sunyoung (김선영)

Welcome to the AI-hardware & Memory Application Design Lab! Our research covers a wide range of areas, from Neuromorphic hardware to AI algorithms. We especially focus on Neuromorphic hardware, PIM (Process-In-Memory) systems, and Algorithm-Hardware co-optimization. Our work involves leveraging different types of memory devices, including charge-based memory (SRAM and DRAM) and resistive memory (PRAM, MRAM, and Skyrmion). The main research area starts from a basic understanding of artificial neural networks, followed by hardware implementation and algorithm analysis of artificial neural networks. In addition, we plan to simultaneously conduct research on memory and I/O circuits, and in-memory computing, which are closely related to this field.

인공지능 및 메모리응용 연구실의 주된 연구분야는 인공신경망의 기본 이해에서부터 시작하여, 인공신경망의 하드웨어 구현 및 알고리즘 분석입니다. 또한, 이 분야와 밀접한 연관이 있는 메모리 및 입출력 회로, 인메모리 컴퓨팅에 대한 연구를 동시에 진행하려고 합니다.

Energy-Efficient Stochastic Spiking Neural Network Hardware with 8T SRAM Array Utilizing Sub-Threshold Cascaded Current Mirrors and Stochastic CMOS Leaky Integrate-and-Fire Neurons

Dual-Mode 2T1C DRAM Process-In-Memory Architecture for Boolean and MAC Operations

Low Power CMOS Stochastic Bit Based Ising Machine and Its Application to Graph Coloring Problem

Union SRAM: PVT variation Auto-Compensated, bit precision configurable current mode 8T SRAM In memory MAC macro

All Stochastic-Spiking Neural Network (AS-SNN): Noise Induced Spike Pulse Generator for Input and Output Neurons With Resistive Synaptic Array

8T-SRAM Based Process-In-Memory (PIM) System With Current Mirror for Accurate MAC Operation

Noise Immunity-Enhanced Capacitance Readout Circuit for Human Interaction Detection in Human Body Communication Systems

SIMO DC-DC Converter with Low-Complexity Hybrid Comparator-Charge Control

Energy Efficient Distance Computing: Application to K-Means Clustering

An Accurate Time-Based MPPT Circuit With Two-Period Tracking Algorithm and Convergence Range Averaging Technique for IoT Applications

A 0.5 V 10 b 3 MS/s 2-then-1b/cycle SAR ADC with Digital-based Time-Domain Reference and Dual-Mode Comparator

A Reference-Sampling Based Calibration-Free Fractional-N PLL with a PI-Linked Sampling Clock Generator

Distance Computation Based on Coupled Spin-Torque Oscillators: Application to Image Processing

SBSNN: Stochastic-bits enabled binary spiking neural network with on-chip learning for energy efficient neuromorphic computing at the edge

Revisiting stochastic computing in the era of nanoscale nonvolatile technologies

Perspective: Stochastic magnetic devices for cognitive computing

Biased random walk using stochastic switching of nanomagnets: Application to SAT solver

Stochastic spin-orbit torque devices as elements for bayesian inference

Magnetoelectric oxide based stochastic spin device towards solving combinatorial optimization problems

Coupled spin-torque nano-oscillator-based computation: A simulation study

Ising computation based combinatorial optimization using spin-Hall effect (SHE) induced stochastic magnetization reversal

Proposal for an all-spin artificial neural network: Emulating neural and synaptic functionalities through domain wall motion in ferromagnets

STT-SNN: A spin-transfer-torque based soft-limiting non-linear neuron for low-power artificial neural networks

A 1.2 V 30 nm 3.2 Gb/s/pin 4 Gb DDR4 SDRAM with dual-error detection and PVT-tolerant data-fetch scheme

Coupled 7T 1C SRAM based in-memory computing architecture with gain/offset error auto-compensated SAR ADC

Stochastic Switching of SHE-MTJ as a Natural Annealer for Efficient Combinatorial Optimization

Low-power approximate convolution computing unit with domain-wall motion based" spin-memristor" for image processing applications

Computing with coupled spin torque nano oscillators

A Heterogeneous Dual DLL and Quantization error minimized ZQ calibration for 30nm 1.2 V 4Gb 3.2 Gb/s/pin DDR4 SDRAM

A mixed-structure delay locked-loop with wide range and fast locking

A register controlled delay locked loop using a TDC and a new fine delay line scheme

Apparatus and method for reducing di/dt

Bi-directional multi-mode charge pump

Apparatus and method for reducing di/dt during power wake-up

Electronic device having a delay locked loop, and memory device having the same

Duty cycle error detection device and duty cycle correction device having the same

Memory device and method for driving the same

Semiconductor memory device with signal reshaping and method of operating the same

Input buffer and memory device including the same

확률적 비트 기반의 스파이킹 신경망 장치 및 이를 구비하는 컴퓨팅 장치

오류의 자동 보상 기능을 갖는 PIM 시스템 및 이를 구비하는 컴퓨팅 장치

PIM 시스템 및 이를 구비하는 컴퓨팅 장치

전류 미러를 이용한 MAC 연산 장치 및 이를 구비하는 PIM 시스템

AI-hardware & Memory Application Design Lab

교수님 소개

심용

연구실 소개

연구실 키워드

알럼나이가 간 회사

연구실 지원 방법

대우 조건

연도별 논문 인용수

저널 & 학회 논문 출판 수

연구실 논문 목록

Energy-Efficient Stochastic Spiking Neural Network Hardware with 8T SRAM Array Utilizing Sub-Threshold Cascaded Current Mirrors and Stochastic CMOS Leaky Integrate-and-Fire Neurons

Dual-Mode 2T1C DRAM Process-In-Memory Architecture for Boolean and MAC Operations

Low Power CMOS Stochastic Bit Based Ising Machine and Its Application to Graph Coloring Problem

연구실 보유 특허

대학별 입시끈

우리 연구실 모집

교수님 소개

심용

연구실 키워드

알럼나이가 간 회사

연구실 지원 방법

대우 조건

연도별 논문 인용수

저널 & 학회 논문 출판 수

연구실 논문 목록

Energy-Efficient Stochastic Spiking Neural Network Hardware with 8T SRAM Array Utilizing Sub-Threshold Cascaded Current Mirrors and Stochastic CMOS Leaky Integrate-and-Fire Neurons

Dual-Mode 2T1C DRAM Process-In-Memory Architecture for Boolean and MAC Operations

Low Power CMOS Stochastic Bit Based Ising Machine and Its Application to Graph Coloring Problem

연구실 보유 특허

최근 3년간 연구실적 높은 연구실

대학별 입시끈

우리 연구실 모집