Embedded Systems and Computer Architecture Labs (ESCA) at Korea University focuses on AI accelerators, NPUs (Neural Processing Units), IoTs, computer architecture, multi- & many-core, parallel programming, hardware security, and virtualization.

Secure MSM Outsource Computation for Zero-knowledge Proof

HBM-aware Number Theoretic Transform Accelerator for Zero-Knowledge Proof

Cross-Filter Structured Pruning for Efficient Sparse CNN Acceleration

SkipNZ: Non-Zero Value Skipping for Efficient CNN Acceleration

Designing and Evaluating HBM-aware NTT Accelerator

Efficiently Exploiting Inference Parallelism in Two-Sided Sparse CNNs for a High-Speed, Low-Cost Accelerator

SparsePIM: An Efficient HBM-Based PIM

TPU as Cryptographic Accelerator

StarSPA: Stride-Aware Sparsity Compression for Efficient CNN Acceleration

Optimization of Microarchitecture and Dataflow for Sparse Tensor CNN Acceleration

Vizard: Passing over Profiling-Based Detection by Manipulating Performance Counters

GhostLeg: Selective Memory Coalescing for Secure GPU Architecture

Continual Learning with Speculative Backpropagation and Activation History

Revoking Speculative Cache Updates Exploiting Write-Back Buffer

Eavesdropping Vulnerability and Countermeasure in Infrared Communication for IoT Devices

A Low-Overhead Defense Mechanism Pinpointing Cache Side-Channel Attacks

A Secure and Flexible FPGA-based Blockchain System for IIoTs

Speculative Backpropagation for CNN Parallel Training

FPGA based Enclave for Industrial IoT Blockchain Systems

Blockchain based End-to-end Tracking System for Distributed IoT Intelligence Application Security Enhancement

Speculative Backpropagation in Deep Neural Network for Parallel Training

DIoTA: Decentralized-Ledger-based Framework for Data Authenticity Protection in IoT Systems

SafeDB: Spark Acceleration on FPGA Clouds with Enclaved Data Processing and Bitstream Protection

FPGALedger: FPGA based Decentralized Ledger for Enterprise Applications

DQN-based OpenCL Workload Partition for Performance Optimization

A Low-Cost Surveillance and Information System for Museum Using Visible Light Communication

FASTEN: An FPGA-based Secure System for Big Data Processing

Architectural Protection of Application Privacy Against Software and Physical Attacks in Untrusted Cloud Environment

Evaluating Coherence-exploiting Hardware Trojan

A Workflow Scheduling Technique Using Genetic Algorithm in Spot Instance-Based Cloud

A Scheduling Algorithm with Dynamic Properties in Mobile Grid

Privacy Preserving Large Scale DNA Read-mapping in MapReduce Framework using FPGA

End-to-End Big Data Processing Protection in Cloud Environment using Black Boxes - An FPGA Approach

Estimated Interval-based Checkpointing (EIC) on Spot Instances in Cloud Computing

PFC: Privacy Preserving FPGA Cloud - a Case Study of MapReduce

Leveraging Process Variation for Performance and Energy: In the Perspective of Overclocking

Scalable and leaderless Byzantine consensus in cloud computing environments

Unstructured deadlock detection technique with scalability and complexity-efficiency in clouds

Performance evaluation of many-core systems: case study with TILEPro64

Accelerating Histograms of Oriented Gradients Descriptor Extraction for Pedestrian Recognition

Multi-Processor Architectural Support for Protecting Virtual Machine Privacy in Untrusted Cloud Environment

Pipelined CPU Design with FPGA in Teaching Computer Architecture

Architectural Support of Multiple Hypervisors over Single Platform for Enhancing Cloud Computing Security

Using Virtual Platform in Embedded System Education

A Low-Overhead Scheduling Scheme based on Genetic Algorithm in Mobile Grids

Unsupervised Lexical Entry Acquisition Model based on Representation of Human Mental Lexicon

Latch-based FPGA Emulation Method for Design Verification: a case study with a microprocessor

PolyHype: Towards Poly-Hypervisor Platform for Cloud Computing

Mobility-aware Balanced Scheduling Algorithm in Mobile Grid Based on Mobile Agent

A Personalized English vocabulary learning system based on cognitive abilities related to foreign language proficiency

Field programmable gate array-based Haar classifier for accelerating face detection algorithm

Adaptive Service Scheduling for Workflow Applications in Service-Oriented Grid

A Desktop Computer with a Reconfigurable Pentium

An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems

An FPGA-based Pentium in a Complete Desktop System

Coherence Traffic Considered Harmful - An FPGA Approach to Quantifying Coherence Traffic Efficiency on Multiprocessor Systems

Integration of Cache Coherence Protocols for MPSoCs and Coherence Traffic Evaluation using FPGA

Initial Observations of Hardware/Software Co-Simulation using FPGA in Architecture Research

Cache Coherence Support for Non-Shared Bus Architecture on Heterogeneous MP SoCs

Evaluating System-wide Monitoring Capsule Design Using Xilinx Virtex-II Pro FPGA

Construction and Performance Characterization of Parallel Interior Point Solver on 4-way Intel Itanium Multiprocessor System

Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 2

Integrating Cache Coherence Protocols for Heterogeneous Multiprocessor Systems, Part 1

Supporting Cache Coherence in Heterogeneous Multiprocessor Systems

Simulation and modeling of electron-beam lithography for delineating 0.2-um line and space patterns

Supporting cache coherence in heterogeneous multiprocessor systems

Pipelined cpu design with fpga in teaching computer architecture

Diota: Decentralized-ledger-based framework for data authenticity protection in iot systems

An FPGA-based Pentium® in a complete desktop system

Accelerating histograms of oriented gradients descriptor extraction for pedestrian recognition

PFC: Privacy preserving FPGA cloud-a case study of MapReduce

Fasten: An fpga-based secure system for big data processing

Balanced scheduling algorithm considering availability in mobile grid

Eavesdropping vulnerability and countermeasure in infrared communication for IoT devices

Speculative backpropagation for CNN parallel training

Architectural support of multiple hypervisors over single platform for enhancing cloud computing security

Integrating cache coherence protocols for heterogeneous multiprocessor systems. 1

Evaluating coherence-exploiting hardware trojan

Development and evaluation of a STEAM curriculum utilizing Arduino

A low-cost surveillance and information system for museum using visible light communication

A secure and flexible FPGA-based blockchain system for the IIoT

FPGA based blockchain system for industrial IoT

A Workflow Scheduling Technique Using Genetic Algorithm in Spot Instance-Based Cloud.

Leveraging process variation for performance and energy: In the perspective of overclocking

Taeweon Suh

In embedded system-on-a-chip (SoC) applications, the demand for integrating heterogeneous processors onto a single chip is increasing. An important issue in integrating multiple heterogeneous processors on the same chip is to maintain the coherence of their data caches. In this paper, we propose a hardware/software methodology to make caches coherent in heterogeneous multiprocessor platforms with shared memory. Our approach works with any combination of processors that support invalidation-based protocols. As shown in our experiments, up to 58% performance improvement can be achieved with low miss penalty at the expense of adding simple hardware, compared to a pure software solution. Speedup can be improved even further as the miss penalty increases. In addition, our approach provides embedded system programmers a transparent view of shared data, removing the burden of software …

This paper presents a pipelined CPU design project with a field programmable gate array (FPGA) system in a computer architecture course. The class project is a five-stage pipelined 32-bit MIPS design with experiments on the Altera DE2 board. For proper scheduling, milestones were set every one or two weeks to help students complete the project on time. The goal of the project is to educate students effectively via hands-on learning, rather than having them achieve a complete and flawless CPU design. This study reveals that 21 MIPS instructions are enough to achieve the purpose. With the addition in 2010 of the properly enforced scheduling and the FPGA system, many more students successfully completed the class project than was the case in 2009. A student survey and the independent samples t-test reveal the effectiveness of the methodology with the FPGA system. This work differs from previous work in …

It is predicted that more than 20 billion IoT devices will be deployed worldwide by 2020. These devices form the critical infrastructure to support a variety of important applications such as smart city, smart grid, and industrial internet. To guarantee that these applications work properly, it is imperative to authenticate these devices and data generated from them. Although digital signatures can be applied for these purposes, the scale of the overall system and the limited computation capability of IoT devices pose two big challenges. In order to overcome these obstacles, we propose DIoTA, a novel decentralized ledger-based authentication framework for IoT devices. DIoTA uses a two-layer decentralized ledger architecture together with a lightweight data authentication mechanism to facilitate IoT devices and data management. We also analyze the performance and security of DIoTA, and explicitly give the major …

Software simulation has been the predominant method for architects to evaluate microprocessor research proposals. There are three tenets in modeling new designs with software models: simulation speed, model accuracy and model completeness. The increasing complexity of the processor and accelerated trend to have multiple processors on a chip are putting burden on simulators to achieve all tenets mentioned, including accurately capturing OS effects. In this work we perform preliminary experimentation/prototyping with an emulation system which overcomes the tension to satisfy all three requirements. The system is an original Socket-7 based desktop processor system with typical hardware peripherals running modern operating systems such as Fedora Core 4 and Windows XP; however we have inserted a Xilinx Virtex-4 in place of the processor that should sit in the motherboard and have used the Virtex-4 …

Pedestrian recognition is an emerging visual computing application for embedded systems. In one usage model, a vehicle mounted camera acquires image from road and a pedestrian recognition system automatically recognizes and alarms information on the road preventing traffic accidents. Achieving this in software on embedded systems requires significant compute processing for object recognition. In this paper, we identify the hotspot function of the workload on an embedded system that motivates acceleration and present the detailed design of a hardware accelerator for Histograms of Oriented Gradients descriptor extraction. We also quantify the performance and area efficiency of the hardware accelerator. Our analysis shows that hardware acceleration has the potential to improve the hotspot function. As a result, user response time can be reduced significantly.

Privacy is one of the critical concerns that hinder the adoption of public cloud. For storage, encryption can be used to protect user's data. But for outsourced data processing, for example MapReduce, there is no satisfying solution. Users have to trust the cloud service providers totally. In this work, we propose PFC, a FPGA cloud for privacy preserving computation in the public cloud environment. PFC leverages the security feature of the existing FPGAs originally designed for bitstream IP protection and proxy re-encryption for preserving user data privacy. In PFC, cloud service providers are not necessarily trusted, and during outsourced computation, user's data is protected by a data encryption key only accessible by trusted FPGA devices. As an important application of cloud computing, we apply PFC to the popular MapReduce programming model and extend the FPGA based MapReduce pipeline with privacy …

In cloud computing framework, the data security and protection is one of the most important aspects for optimization and concrete implementation. This paper proposes a reliable yet efficient FPGA-based security system via crypto engines and Physical Unclonable Functions (PUFs) for big data applications. Considering that FPGA or GPU-based accelerators are popular in data centers, we believe the proposed approach is very practical and effective method for data security in cloud computing.

The emerging Grid is extending the scope of resources to mobile devices and sensors that are connected through unreliable networks. Nowadays the number of mobile device users is increasing dramatically and the mobile devices provide various capabilities such as location awareness that are not normally incorporated in fixed Grid resources. Nevertheless, mobile devices exhibit inferior characteristics such as poor performance, limited battery life, and unreliable communication, compared to fixed Grid resources. Therefore, the job scheduling and the load balancing are more challenging and sophisticated in mobile Grid environment. This paper presents a novel balanced scheduling algorithm in mobile Grid, taking into account the mobility and availability in scheduling. We analyzed users’ mobility patterns to quantitatively measure the resource availability that is classified into three types: full availability, partial …

Infrared (IR) communication is one of the wireless communication methods mainly used to manipulate consumer electronics devices. Traditional IR devices support only simple operations such as changing TV channels. These days, consumer electronic devices such as smart TV are connected to the internet with the introduction of IoT. Thus, the user’s sensitive information such as credit card number and/or personal information could be entered with the IR remote. This situation raises a new problem. Since TV and the set-top box are visual media, these devices can be used to control and/or monitor other IoT devices at home. Therefore, personal information can be exposed to eavesdroppers. In this paper, we experimented with the IR devices’ reception sensitivity using remotes. These experiments were performed to measure the IR reception sensitivity in terms of distance and position between the device and the remote. According to our experiments, the transmission distance of the IR remote signal is more than 20 m. The experiments also revealed that curtains do not block infrared rays. Consequently, eavesdropping is possible to steal the user’s sensitive information. This paper proposes a simple, practical, and cost-effective countermeasure against eavesdropping, which does not impose any burden on users. Basically, encryption is used to prevent the eavesdropping. The encryption key is created by recycling a timer inside the microcontroller typically integrated in a remote. The key is regenerated whenever the power button on a remote is pressed, providing the limited lifecycle of the key. The evaluation indicates that the XOR-based …

The parallel learning in neural networks can greatly shorten the training time. Its prior efforts were mostly limited to distributing inputs to multiple computing engines. It is because the gradient descent algorithm in the neural network training is inherently sequential. This paper proposes a novel CNN parallel training method for image recognition. It overcomes the sequential property of the gradient descent and enables the parallel training with the speculative backpropagation. We found that the Softmax and ReLU outcomes in the forward propagation for the same labels are likely to be very similar. This characteristic makes it possible to perform the forward and backward propagation simultaneously. We implemented the proposed parallel model with CNNs in both software and hardware, and evaluated its performance. The parallel training reduces the training time by 34% in CIFAR-100 without the loss of the …

Traditional Byzantine consensus in distributed systems requires n ≥ 3 f + 1, where n is the number of nodes. In this paper, we present a scalable and leaderless Byzantine consensus implementation based on gossip , requiring only n ≥ 2 f + 1 nodes. Unlike conventional distributed systems, the network topology of cloud computing systems is often not fully connected, but loosely coupled and layered. Hence, we revisit the Byzantine consensus problem in cloud computing environments, in which each node maintains some number of neighbors, called local view . The message complexity of our Byzantine consensus scheme is O ( n ), instead of O ( n 2 ). Experimental results and correctness proof show that our Byzantine consensus scheme can solve the Byzantine consensus problem safely in a scalable way without a bottleneck and a leader in cloud computing environments.

This paper presents MultiHype, a novel architecture that supports multiple hypervisors (or virtual machine monitors) on a single physical platform by leveraging many-core based cloud-on-chip architecture. A MultiHype platform consists of a control plane and multiple hypervisors created on-demand, each can further create multiple guest virtual machines. Supported at architectural level, a single platform using MultiHype can behave as a distributed system with each hypervisor and its virtual machines running independently and concurrently. As a direct consequence, vulnerabilities of one hypervisor or its guest virtual machine can be confined within its own domain, which makes the platform more resilient to malicious attacks and failures in a cloud environment. Towards defending against resource exhaustion attacks, MultiHype further implements a new cache eviction policy and memory management scheme for …

This systematic methodology maintains cache coherency in a heterogeneous shared-memory multiprocessor system on a chip. It works with any combination of processors that support any invalidation-based protocol, and experiments have demonstrated up to a 51 percent performance improvement, compared to a pure software solution.

Increasing complexity of integrated circuits and IP-based hardware designs have created the risk of hardware Trojans. This paper introduces a new type of threat, a coherence-exploiting hardware Trojan. This Trojan can be maliciously implanted in master components in a system, and continuously injects memory transactions onto the main interconnect. The injected traffic forces the eviction of cache lines, taking advantage of cache coherence protocols. This type of Trojans insidiously slows down the system performance, incurring Denial-of-Service (DoS) attack. We used a Xilinx Zynq-7000 device to implement the Trojan and evaluate its severity. Experiments revealed that the system performance can be severely degraded as much as 258% with the Trojan. A countermeasure to annihilate the Trojan attack is proposed in detail. We also found that AXI version 3.0 supports a seemingly irrelevant invalidation protocol …

The nature of complex modern society inevitably creates intricate problems that can be solved by the computational and logical reasoning. The programming education in Informatics can effectively raise the ability of computational thinking. The paper proposes and evaluates a STEAM curriculum that can draw the interest and attention of students. The curriculum educates the multi-disciplinary knowledge from science, music and informatics, and it was designed to have group discussions with self-directed study. The experiments were performed with grade gifted students in Informatics from elementary schools. The Arduino was used as the experiment environment. The experiment results reveal that the interests in Informatics and programming have been escalated after the STEAM class; 75% of students expressed the surge of interest in computers and 93% of students responded positively to the Arduino-based class. The effectiveness of the experiment outcomes was validated with t-test.

This paper designed and implemented a low-cost surveillance and information system for museums with two new coding schemes using visible light communication. For security, we use a key in place of the clock in the Manchester coding. For the enhanced data transfer, we use the unbalanced time duration for data one and zero. The prototype system was built with two low-cost microcontrollers, an LED, and linear light sensors. With 1-m distance in a dark environment, the maximum data transfer rate was roughly 1.93 kbits/s with a white LED. Under the dark-to-modest ambient brightness of up to 120 lux, the white LEDs were performed well in terms of the transmission distance, compared with LEDs with different colors. The experiments with flashlights reveal that our system can easily detect the prohibited use of flashlight. Experiments with the mobile phones' flashlight also revealed that photographing with the …

Blockchain is a promising solution for Industry 4.0; however, it does not guarantee input data integrity. We propose a field-programmable gate array (FPGA)-based private blockchain system for the industrial Internet of Things, where the transaction generation is performed inside the FPGA in an isolated and enclaved manner.

Industrial IoT (IIoT) is critical for industrial infrastructure modernization and digitalization. Therefore, it is of utmost importance to provide adequate protection of the IIoT system. A modern IIoT system usually consists of a large number of devices that are deployed in multiple locations and owned/managed by different entities who do not fully trust each other. These features make it harder to manage the system in a coherent manner and utilize existing security mechanisms to offer adequate protection. The emerging blockchain technology provides a powerful tool for IIoT system management and protection because the IIoT nature of distributed deployment and involvement of multiple stakeholders fits the design philosophy of blockchain well. Most existing blockchain construction mechanisms are not scalable enough and too heavy for an IIoT system. One promising way to overcome these limitations is utilizing …

Cloud computing is a computing paradigm in which users can rent computing resources from service providers according to their requirements. A spot instance in cloud computing helps a user to obtain resources at a lower cost. However, a crucial weakness of spot instances is that the resources can be unreliable anytime due to the fluctuation of instance prices, resulting in increasing the failure time of users' job. In this paper, we propose a Genetic Algorithm (GA)-based workflow scheduling scheme that can find the optimal task size of each instance in a spot instance-based cloud computing environment without increasing users' budgets. Our scheme reduces total task execution time even if an out-of-bid situation occurs in an instance. The simulation results, based on a before-and-after GA comparison, reveal that our scheme achieves performance improvements in terms of reducing the task execution time on …

Process variation is one of the most important factors to be considered in recent microprocessor design, since it negatively affects performance, power, and yield of microprocessors. However, by leveraging process variation, overclocking techniques can improve performance. As microprocessors have substantial clock cycle time margin for yield, there is enough room for performance improvement by overclocking techniques. In this paper, we adopt the F-overclocking technique, which increases clock frequency without changing supply voltage. Our experimental results show that the F-overclocking technique significantly improves performance as well as energy consumption. In addition, the F-overclocking technique is superior to the conventional overclocking technique which increases clock frequency and supply voltage together in the perspective of energy efficiency and reliability, showing similar performance …

Professor

Embedded Systems and Computer Architecture Labs (ESCA)

교수님 소개

서태원

연구실 소개

연구실 키워드

알럼나이가 간 회사

연구실 지원 방법

대우 조건

연도별 논문 인용수

저널 & 학회 논문 출판 수

연구실 논문 목록

Secure MSM Outsource Computation for Zero-knowledge Proof

HBM-aware Number Theoretic Transform Accelerator for Zero-Knowledge Proof

Cross-Filter Structured Pruning for Efficient Sparse CNN Acceleration

연구실 보유 특허

대학별 입시끈

우리 연구실 모집

교수님 소개

서태원

연구실 키워드

알럼나이가 간 회사

연구실 지원 방법

대우 조건

연도별 논문 인용수

저널 & 학회 논문 출판 수

연구실 논문 목록

Secure MSM Outsource Computation for Zero-knowledge Proof

HBM-aware Number Theoretic Transform Accelerator for Zero-Knowledge Proof

Cross-Filter Structured Pruning for Efficient Sparse CNN Acceleration

연구실 보유 특허

최근 3년간 연구실적 높은 연구실

대학별 입시끈

우리 연구실 모집