The Semiconductor Design Automation (SeDA) Lab, situated within the Department of Electrical Engineering at Ulsan National Institute of Science and Technology (UNIST), concentrates on the research and development of computer-aided design (CAD) solutions tailored for SoC & VLSI. The lab aims to establish electronic design automation (EDA) frameworks to facilitate the rapid production of advanced digital IPs/chips, while optimizing power, performance, area, and cost (PPAC). Research is being expanded to encompass (1) next-generation integrated chip (IC) structures, including 3D ICs, chiplet-based 2.5D ICs, and advanced technology nodes; and (2) the integration of AI with EDA, exploring both AI for EDA (AI/ML application to EDA) and EDA for AI (EDA framework for AI chip design).

울산과학기술원(UNIST) 전기전자공학과에 위치한 반도체 설계 자동화(SeDA) 연구실은 SoC 및 VLSI용 컴퓨터 지원 설계(CAD) 솔루션 연구 개발에 중점을 둔다. 주요 목표는 전력, 성능, 면적 및 비용(PPAC)을 최적화하면서 고급 디지털 IP/칩의 신속한 생산을 지원하는 전자 설계 자동화(EDA) 프레임워크를 구축하는 것이다. 연구 범위는 (1) 3D IC, 칩렛 기반 2.5D IC 및 첨단 기술 노드와 같은 차세대 집적 회로(IC) 구조와 (2) AI for EDA(EDA에 대한 AI/ML 적용) 및 EDA for AI(AI 칩 설계를 위한 EDA 프레임워크)를 포함하는 AI와 EDA의 통합으로 확장되고 있다.

Critical-Path-Centric 3D IC Placement for Timing Optimization

Breaking Standard Cell Margin Constraints for Area-Efficient VLSI Design

Standard Cell Layout Generation: Methodological Evolution and Architectural Impacts

SMT-Based Optimal Transistor Folding and Placement for Standard Cell Layout Generation

Active BSCDN Benchmark Framework with Backside-Compatible CNFET Logic Technology

A Unified Design Flow for Homogeneous and Heterogeneous 3D Integration with Fine-Pitch Hybrid Bonding

Priority-Aware Routing Optimization with Full-Path Delay Prediction Using Machine Learning

Timing-Driven Macro Placement with Connectivity-Aware Clustering

Mitigating Routability Problems in Complementary-FET-based VLSI Designs

Timing-Driven Detailed Placement with Unsupervised Graph Learning

Clustering-Driven Bonding Terminal Legalization with Reinforcement Learning for F2F 3D ICs

PPA-Aware Tier Partitioning for 3D IC Placement with ILP Formulation

Memristive Logic-in-Memory Implementation with Area Efficiency and Parallelism

3T1R Memristor Crossbar Architecture for Diverse Logic Implementation

Double-Row Flip-flop Design Under Advanced Technology and Its IC-Level Effects

Graph Neural Network-Based Detailed Placement Optimization Framework

Design-Technology Co-Optimization with Standard Cell Layout Generator for Pin Configurations

Timing-Aware Tier Partitioning for 3D ICs With Critical Path Consideration

DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool

Tightly Linking 3D via Allocation towards Routing Optimization for Monolithic 3D ICs

A Systematic Removal of Minimum Implant Area Violations under Timing Constraint

Safety Verification of AMS Circuits with Piecewise-Linear System Reachability Analysis

Challenges on DTCO Methodology Towards Deep Submicron Interconnect Technology

Minimum Implant Area-Aware Threshold Voltage Refinement in Pre-Placement

Pseudo-3D Approaches for Commercial-Grade RTL-to-GDS Tool Flow Targeting Monolithic 3D ICs

RTL-to-GDS Design Tools for Monolithic 3D ICs Built with Carbon Nanotube Transistors and Resistive Memory

RTL-to-GDS Tool Flow and Design-for-Test Solutions for Monolithic 3D ICs

Architecture, Chip, and Package Co-design Flow for 2.5D Integration of Reusable IP Chiplets

Built-in Self-Test for Inter-Layer Vias in Monolithic 3D ICs

Design Space Exploration of Power Delivery in Heterogeneous Integration

Enabling Heterogeneous IP Reuse with Interposer-based 2.5D ICs and Custom Interface Protocol

Structure Optimizations of Neuromorphic Computing Architectures for Deep Neural Networks

Synthesizing Asynchronous Circuits Toward Practical Use

Comprehensive Technique for Designing and Synthesizing TSV Fault-Tolerant 3D Clock Trees

Fault Coverage and Resource Analysis for Diverse Structures of Clock TSV Fault-Tolerant Units in 3D ICs

DTOC-P: Deep-learning-driven Timing Optimization using Commercial EDA Tool with Practicality Enhancement

Comprehensive Physical Design Flow Incorporating 3D Connections for Monolithic 3D ICs

Eliminating Minimum Implant Area Violations With Design Quality Preservation

Speeding-up Neuromorphic Computation for Neural Networks: Structure Optimization Approach

Built-in self-test and fault localization for inter-layer vias in monolithic 3D ICs

Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements

Clock Delivery Network Design and Analysis for Interposer-based 2.5D Heterogeneous Systems

Allocation of Always-On State Retention Storage for Power Gated Circuits - Steady State Driven Approach

Design Flow for Active Interposer-Based 2.5D ICs and Study of RISC-V Architecture with Secure NoC

Architecture, Chip, and Package Co-design Flow for Interposer-based 2.5D Chiplet Integration Enabling Heterogeneous IP Reuse

Advances in Design and Test of Monolithic 3D ICs

Hybrid asynchronous circuit generation amenable to conventional EDA flow

Synthesis of TSV Fault-Tolerant 3D Clock Trees

PPA-Driven Multi-Bit Flip-Flop Clustering Based on Minimum-Cost Maximum-Flow Algorithm

Multi-Objective Logic Optimization with Diffusion Model

Logic Partitioning Methodology for Utilizing Active Backside Layers

Dataflow-Aware Placement Optimization for Digital Compute-in-Memory (DCIM) Using H-Tree-Like Adder Tree Organization

Logic Optimization via Reinforcement Learning–Guided Gate Transformation

Timing-Driven Hierarchical Gate Sizing with Reinforcement Learning

Efficient 3D IC CTS Flow with Commercial EDA Tools

Unsupervised Learning-Based Legalization with Graph Neural Network

Design-Technology Co-Optimization for Standard Cell Pin Length Modulation

Chiplet Placement with Sequence Pair Based Tree and Branch-and-Bound Method Considering Chiplet Ordering

Deep Learning Driven Pre-Route Arc Length Prediction Considering Routing Priority

Logic-in-Memory Technology Mapping Framework for Memristor Crossbar with Maximized Parallelism

클록 분배망의 독립적 배선 구조를 이용한 클록 신호 및 로직 신호의 완전 분리형 반도체 장
치
및 시스템

Architecture, chip, and package codesign flow for interposer-based 2.5-D chiplet integration enabling heterogeneous IP reuse

Architecture, chip, and package co-design flow for 2.5 D IC design enabling heterogeneous IP reuse

Design flow for active interposer-based 2.5-D ICs and study of RISC-V architecture with secure NoC

Pseudo-3D approaches for commercial-grade RTL-to-GDS tool flow targeting monolithic 3D ICs

Physical Design for 3D Integrated Circuits - Design Methodology for TSV-Based 3D Clock Networks (Chapter 7)

Built-in self-test for inter-layer vias in monolithic 3D ICs

Synthesis of TSV fault-tolerant 3-D clock trees

Pseudo-3d physical design flow for monolithic 3d ics: Comparisons and enhancements

RTL-to-GDS tool flow and design-for-test solutions for monolithic 3D ICs

Advances in design and test of monolithic 3-D ICs

DTOC-P: deep-learning-driven timing optimization using commercial EDA tool with practicality enhancement

Comprehensive physical design flow incorporating 3-D connections for monolithic 3-D ICs

Structure optimizations of neuromorphic computing architectures for deep neural network

Synthesizing asynchronous circuits toward practical use

A systematic removal of minimum implant area violations under timing constraint

Clock delivery network design and analysis for interposer-based 2.5-d heterogeneous systems

Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees

Semiconductor Design Automation Lab.

교수님 소개

박희천

연구실 소개

연구실 키워드

알럼나이가 간 회사

연구실 지원 방법

대우 조건

연도별 논문 인용수

저널 & 학회 논문 출판 수

연구실 논문 목록

Critical-Path-Centric 3D IC Placement for Timing Optimization

Breaking Standard Cell Margin Constraints for Area-Efficient VLSI Design

Standard Cell Layout Generation: Methodological Evolution and Architectural Impacts

연구실 보유 특허

대학별 입시끈

우리 연구실 모집

교수님 소개

박희천

연구실 키워드

알럼나이가 간 회사

연구실 지원 방법

대우 조건

연도별 논문 인용수

저널 & 학회 논문 출판 수

연구실 논문 목록

Critical-Path-Centric 3D IC Placement for Timing Optimization

Breaking Standard Cell Margin Constraints for Area-Efficient VLSI Design

Standard Cell Layout Generation: Methodological Evolution and Architectural Impacts

연구실 보유 특허

최근 3년간 연구실적 높은 연구실

대학별 입시끈

우리 연구실 모집