Dongkyu Park

Seokryong Yoon

Seok soo Yoon

Jinhan Kim

Wonho Park

Dongsuk Shin

Wookkee Han

Janghoon Song

Pulkit Jain

Sunghoon Ahn

Jimin Shin

Inho Lee

Kyunghoon Chung

Amit Mittal

Hyunsoo Chae

Jinwoo Kim

Jinseock Ma

Daejung Shin

Ja-Beom Koo

Sunghwa Ok

Taeyoon Kim

Yongtae Kim

Sangdon Jung

Hyunho Chu

Kisoo Kim

Woonhyung heo

Phi-Hung Pham

Young-Ho Kwak

Moo-Young Kim

Dong Seok Kim

Debashis Dhar

Kyeong-min Kim

Inhwa Jung

Jihwan Kim

Hong-Seung Yang

Hyun Woo Lee

Byung-Wook Ahn

Nam-Wook Cho

Minyoung Song

Soo-Bin Lim

Jeong Lee

Sanghun Lee

Xu Kuo

Younghun Baek

Jung-Taek You

Jungmoon Kim

Junyoung Song

Hokyu Lee

Heejun Kim

Changsung Choi

Jayoung Kim

GyungMin Kim

Jaeseon Shim

Youngtae Kim

Sun Myung Choi

Sewook Hwang

Sang-Geun Bae

Dongyoon Kim

Yangho Seo

Doyoun Kim

Aurangozeb

Sungjun Moon

Sangsu Lee

Jinseok Oh

Byunggun Joung

Choonghwan Lee

Jaehun Jun

Minseob Shim

Minho Park

Eunhee Kim

Junwon Jeong

Yeonho Lee

Youngbog Yoon

Junyoung Maeng

Yunsoo Park

Minseob Lee

Jeewan Lee

Wonkee Park

Dongju Lim

Chaegang Lim

Jaegeun Song

Hyunsu Park

Jeongsik Yoo

Minsu Jeong

Changhun Park

Kungryun Yoon

Eunji Lee

Inho Park

Yoonjae Choi

Seokwon Jang

Jaewon Ryu

Hyoshin Kang

Jonghyuck Choi

Jincheol Sim

Yohan Choi

Sungho Cho

Youngwook Kwon

Hyunjin Kim

Seokjin Kim

Seokhee Han

The Advanced Integrated System Lab, within the Department of Electronics Engineering at Korea University, focuses on Clock Generators (PLL, DLL, SSCG), Wireline Transceivers (SERDES, Display, Memory, Optical), Power Management (Energy Harvesting, DC-DC), ADC (Sensor ROIC, Nyquist ADC), Probabilistic Computing, and Security (PUF, TRNG).

고려대학교 전자공학과에 소속된 Advanced Integrated System Lab은 클록 생성기(PLL, DLL, SSCG), 유선 트랜시버(SERDES, 디스플레이, 메모리, 광통신), 전력 관리(에너지 하베스팅, DC-DC), ADC(센서 ROIC, 나이퀴스트 ADC), 확률적 컴퓨팅 및 보안(PUF, TRNG) 분야에 중점을 둔다.

A 100-nW 9.1-ENOB 20-kS/s SAR ADC for portable pulse oximeter

A 7.5 Gb/s referenceless transceiver for UHDTV with adaptive equalization and bandwidth scanning technique in 0.13 µm CMOS process

A 0.5 V 10-bit 3 MS/s SAR ADC with adaptive-reset switching scheme and near-threshold voltage-optimized design technique

An antiharmonic, programmable, DLL-based frequency multiplier for dynamic frequency scaling

A DLL-based quadrature clock generator with a 3-stage quad delay unit using the sub-range phase interpolator for low-jitter and high-phase accuracy DRAM …

A novel architecture for block interleaving algorithm in MB-OFDM using mixed radix system

A CMOS magnetic Hall sensor using a switched biasing amplifier

A 2.4–8 GHz phase rotator delay-locked loop using cascading structure for direct input–output phase detection

A 140-Mb/s to 1.82-Gb/s continuous-rate embedded clock receiver for flat-panel displays

Wide frequency range duty cycle correction circuit for DDR interface

Analysis of the TEG Maximum Power Point Tracking Operation with Continuously Scalable-Conversion-Ratio SC Converter

Analysis of the Power Conversion Modes for Power-Efficient Energy Harvesting Interfaces

A 0.004-mm Portable Multiphase Clock Generator Tile for 1.2-GHz RISC Microprocessor

A Modulator-Based Spread-Spectrum Clock Generator with Digital Compensation and Calibration for Phase-Locked Loop Bandwidth

A 9 Gb/s/ch transceiver with reference-less data-embedded pseudo-differential clock signaling for graphics memory interfaces

A Single-Input-Four-Output (SIFO) Switched-Capacitor DC-DC Converter with Ordered-Sequential Switching

A periodically refreshed capacitive floating level shifter for conditional switching applications

An area-efficient and wide-range inter-signal skew compensation scheme with the embedded bypass control register operating as a binary search algorithm for DRAM …

An 11.2-Gb/s LVDS receiver with a wide input range comparator

A 2-Gb/s/ch data-dependent swing-limited on-chip signaling for single-ended global I/O in SDRAM

A DC-DC Converter With Voltage-Mode PWM Control

A DC–DC boost converter with variation-tolerant MPPT technique and efficient ZCS circuit for thermoelectric energy harvesting applications

A 1-mW solar-energy-harvesting circuit using an adaptive MPPT with a SAR and a counter

Analog Front-End Design Techniques and Method for Saturation of Hemoglobin with Oxygen Sensor

Ultra-Low Power Pulse Oximeter SoC Design with 32.768 kHz Clock Source

366-kS/s 1.09-nJ 0.0013-mm2 Frequency-to-Digital Converter Based CMOS Temperature Sensor Utilizing Multiphase Clock

위상 회전자를 이용한 LPDDR5 용 1-3.75㎓ 디지털 지연 고정 루프 (DLL)

A 6-bit 2.5-GS/s time-interleaved analog-to-digital converter using resistor-array sharing digital-to-analog converter

2014 IEEE Executive Staff

3-Gb/s high-speed true random number generator using common-mode operating comparator and sampling uncertainty of D flip-flop

A Slew-Rate/Impedance-Controlled Output Driver With Single-Cycle Compensation Time

임베디드 응용 프로그램 성능 분석

Wide input range hybrid DC-DC conversion system for solar energy harvesting

A 20-Gb/s/pin 0.42-pJ/b Single-Ended Receiver with Ping-Pong Self-Referencing Technique

A 5-GHz subsampling PLL-based spread-spectrum clock generator by calibrating the frequency deviation

A Portable and Input-Duty-Independent Multiphase Clock Generator

A regulated charge pump with a low-power integrated optimum power point tracking algorithm for indoor solar energy harvesting

A 0.99-pJ/b 15-Gb/s counter-based adaptive equalizer using single comparator in 28-nm CMOS

An add-on type real-time jitter tolerance enhancer for digital communication receivers

A 0.31–1 GHz fast-corrected duty-cycle corrector with successive approximation register for DDR DRAM applications

A low-power small-area/spl plusmn/7.28-ps-jitter 1-GHz DLL-based clock generator

A 38.1 fJ/Bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation

A 25 Gb/s wireline receiver with feedforward and feedback equalizers at analog front-end

Self-powered 30 µW to 10 mW piezoelectric energy harvesting system with 9.09 ms/V maximum power point tracking time

An 8-Bit 400-MS/s 1-Then-2-Bit/Cycle SAR ADC With Comparator Rotation-Based Input-Independent Background Offset Calibration

IDEC Journal of Integrated Circuits And Systems

A 10 Gb/s Single-Ended Receiver Using Time Gap Sense Amplifier for Next-Generation HBM

A 0.76-1.75 V 0.35 mm² Fast Adaptive Digital Voltage Regulator with Dual Loop Controls

A 1-3.2 GHz 0.6 mW/GHz Duty-Cycle-Corrector Using Bangbang Duty-Cyle-Detector

An on-chip soft-start technique of current-mode DC-DC converter for biomedical applications

A single-input four-output (SIFO) AC–DC rectifying system for vibration energy harvesting

Piecewise linear modulation technique for spread spectrum clock generation

센서 기반 헤모글로빈의 산소 포화도 측정을 위한 아날로그 프런트 엔드 설계 기술 및 방법

A 7 ps Jitter 0.053 mm Fast Lock All-Digital DLL With a Wide Range and High Resolution DCC

A 90.2% peak efficiency multi-input single-inductor multi-output energy harvesting interface with double-conversion rejection technique and buck-based dual …

30-Gb/s 1.11-pJ/bit single-ended PAM-3 transceiver for high-speed memory links

PVT variation tolerant current source with on-chip digital self-calibration

A four-phase hybrid step-up/down converter with RMS inductor current reduction and delay-based zero-current detection

A low-jitter open-loop all-digital clock generator with two-cycle lock-time

A 0.45 pJ/b 24 Gb/s NRZ receiver data-path using half-baud-rate duobinary sampling

An automotive 12 V-to-1.2 V integrated switched-capacitor DC–DC converter for improved load transient response

A 10 Gbits/s/pin DFE-Less Graphics DRAM Interface With Adaptive-Bandwidth PLL for Avoiding Noise Interference and CIJ Reduction Technique

Design of the digitally controlled phase locked loops with 1 st order FIR loop filter

A single-inductor eight-channel output DC–DC converter with time-limited power distribution control and single shared hysteresis comparator

A 1.3–4-GHz quadrature-phase digital DLL using sequential delay control and reconfigurable delay line

A low-voltage high-efficiency voltage doubler for thermoelectric energy harvesting

Single-ended PAM-4 transmitters with data bus inversion and ZQ calibration for high-speed memory interfaces

A 0.458-pJ/bit 24-Gb/s/pin capacitively driven PAM-4 transceiver with PAM-based crosstalk cancellation for high-density die-to-die interfaces

A 0.15 V input energy harvesting charge pump with dynamic body biasing and adaptive dead-time for efficiency improvement

저전력ㆍ광대역 동작을 갖는 DisplayPort 용 직렬화/병렬화 회로

A 10bit 1MS/s 0.5 mW SAR ADC with double sampling technique

A dual-mode continuously scalable-conversion-ratio SC energy harvesting interface with SC-based PFM MPPT and flying capacitor sharing scheme

A single-ended NRZ receiver with gain-enhanced active-inductive CTLE and reference-selection DFE for memory interfaces

A 33-Gb/s/pin 1.09-pJ/bit single-ended PAM-3 transceiver with ground-referenced signaling and time-domain decision technique for multi-chip module memory …

A 7.7 mW/1.0 ns/1.35 V delay locked loop with racing mode and OA-DCC for DRAM interface

A 56-Gb/s PAM-4 receiver using time-based LSB decoder and S/H technique for robustness to comparator voltage variations

A 42 nJ/conversion on-demand state-of-charge indicator for miniature IoT Li-ion batteries

A 16-Gb/s NRZ receiver with 0.0019-pJ/bit/dB 1-tap charge-redistribution DFE

A four-phase time-based switched-capacitor LDO with 13-ns settling time at 0.5-V input for energy-efficient computing in SoC applications

PAM-4 receiver with 1-tap DFE using clocked comparator offset instead of threshold voltages for improved LSB BER performance

A fully integrated dual-output continuously scalable-conversion-ratio SC converter for battery-powered IoT applications

An energy-efficient fast maximum power point tracking circuit in an 800-μW photovoltaic energy harvester

A 101.6-dB-SNDR fully dynamic zoom ADC using miller-compensated floating inverter amplifiers

A 7-bit 1.15-GS/s 2.6-bit/cycle asynchronous SAR ADC using comparator decision skip technique with background offset calibration

A 3.5 GHz spread-spectrum clock generator with a memoryless Newton-Raphson modulation profile

Exploiting thread‐level parallelism in lockstep execution by partially duplicating a single pipeline

Design and implementation of backtracking wave-pipeline switch to support guaranteed throughput in network-on-chip

A wireline transceiver with 3-bit per symbol using common-mode NRZ and differential-mode PAM-4 signaling techniques

Openmp and compilation issue in embedded applications

A capacitively coupled CT Δ σm with chopping artifacts rejection for sensor readout ICs

Transactions/Journals Department

12-Gb/s over four balanced lines utilizing NRZ braid clock signaling with no data overhead and spread transition scheme for 8K UHD intra-panel interfaces

A 1.62–5.4-Gb/s receiver for displayport version 1.2 a with adaptive equalization and referenceless frequency acquisition techniques

In-cell self-capacitive-type mobile touch system and embedded readout circuit in display driver IC

An 11-b 100-MS/s fully dynamic pipelined ADC using a high-linearity dynamic amplifier

A high-voltage dual-input buck converter achieving 52.9% maximum end-to-end efficiency for triboelectric energy-harvesting applications

A 32-Gb/s dual-mode transceiver with one-tap FIR and two-tap IIR RX only equalization in 65-nm CMOS technology

A 25-Gb/s single-ended PAM-4 transmitter with iPWM-based FFE and RLM-matched voltage-mode driver for high-speed memory interfaces

A 6-bit 3.6-GS/s 4-Channel Time-Interleaved ADC With Front-Rank MSB Decision and 2-Then-1.5-bit/Cycle Architecture

Advanced Integrated Systems Lab

교수님 소개

김철우

연구실 소개

연구실 키워드

알럼나이가 간 회사

연구실 지원 방법

대우 조건

연도별 논문 인용수

저널 & 학회 논문 출판 수

연구실 논문 목록

A 20-Gb/s/pin 0.42-pJ/b Single-Ended Receiver with Ping-Pong Self-Referencing Technique

A 6-bit 3.6-GS/s 4-Channel Time-Interleaved ADC With Front-Rank MSB Decision and 2-Then-1.5-bit/Cycle Architecture

A 38.1 fJ/Bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation

연구실 보유 특허

대학별 입시끈

우리 연구실 모집

교수님 소개

김철우

연구실 키워드

알럼나이가 간 회사

연구실 지원 방법

대우 조건

연도별 논문 인용수

저널 & 학회 논문 출판 수

연구실 논문 목록

A 20-Gb/s/pin 0.42-pJ/b Single-Ended Receiver with Ping-Pong Self-Referencing Technique

A 6-bit 3.6-GS/s 4-Channel Time-Interleaved ADC With Front-Rank MSB Decision and 2-Then-1.5-bit/Cycle Architecture

A 38.1 fJ/Bit Capacitive-Latch True Random Number Generator Featuring Both Autozeroed Inverter Mismatch and Accelerated Evaluation

연구실 보유 특허

최근 3년간 연구실적 높은 연구실

대학별 입시끈

우리 연구실 모집