Jung Sungyu

Myungguk Lee

Yeom Changhun

An Jihoon

Anik Biswas

Joonbeom Kweon

Yaejoon Huh

Lee Jaewoo

Sungmin Lim

Minsoo Choi

Sooeun Lee

Seungho Han

Kwangmin Kim

Jaeyoung Seo

Ikho Lee

BEVIL, also known as Broadband Electronics by Virtual Intelligence Laboratory (가상지능기반 광대역전자회로 설계 연구실) at POSTECH, is seeking highly motivated undergraduate research interns and integrated M.S.–Ph.D. students. The lab focuses on research in Artificial Intelligence (AI Programming), Analog Circuit Design Automation, and Analog Circuit Design (Hardware-focused), including Circuit Design and Electronic Design Automation (EDA).

포스텍의 BEVIL(가상지능기반 광대역전자회로 설계 연구실)은 의욕적인 학부 연구 인턴 및 통합 석박사과정 학생들을 찾고 있습니다. 본 연구실은 인공지능(AI 프로그래밍), 아날로그 회로 설계 자동화, 아날로그 회로 설계(하드웨어 중심), 회로 설계 및 전자 설계 자동화(EDA) 분야의 연구에 중점을 둡니다.

A 10-Gb/s compact low-power serial I/O with DFE-IIR equalization in 65-nm CMOS

5.8 A 9.3 nW all-in-one bandgap voltage and current reference circuit

5.7 A 29nW bandgap reference circuit

A 192-pW Voltage Reference Generating Bandgap– With Process and Temperature Dependence Compensation

A 4Gb/s/ch 356fJ/b 10mm equalized on-chip interconnect with nonlinear charge-injecting transmit filter and transimpedance receiver in 90nm CMOS

An energy-efficient equalized transceiver for RC-dominant channels

Equalized interconnects for on-chip networks: Modeling and optimization framework

A FIR-embedded phase interpolator based noise filtering for wide-bandwidth fractional-N PLL

A low-power wide dynamic-range current readout circuit for ion-sensitive FET sensors

Current-mode transceiver for silicon interposer channel

A single-chip 64-channel ultrasound RX-beamformer including analog front-end and an LUT for non-uniform ADC-sample-clock generation

An analog-digital hybrid RX beamformer chip with non-uniform sampling for ultrasound medical imaging with 2D CMUT array

Circuits and methods for DFE with reduced area and power consumption

A delay locked loop with a feedback edge combiner of duty-cycle corrector with a 20%–80% input duty cycle for SDRAMs

An 80 mV-swing single-ended duobinary transceiver with a TIA RX termination for the point-to-point DRAM interface

5.5 A quadrature relaxation oscillator with a process-induced frequency-error compensation loop

24.8 an analog-digital-hybrid single-chip RX beamformer with non-uniform sampling for 2D-CMUT ultrasound imaging to achieve wide dynamic range of delay and small chip area

A 0.65-to-10.5 Gb/s reference-less CDR with asynchronous baud-rate sampling for frequency acquisition and adaptive equalization

18.8 A 192pW Hybrid Bandgap-V th Reference with Process Dependence Compensated by a Dimension-Induced Side-Effect

An 84.6-dB-SNDR and 98.2-dB-SFDR residue-integrated SAR ADC for low-power sensor applications

A Self-Supervised Learning of a Foundation Model for Analog Layout Design Automa…

A Fast Design Optimization of On-Chip Equalizing Links Using Particle Swarm Opti…

Review on Resistive Termination Techniques Driven by Wireline Channel Behaviors

A Self-Supervised Learning of a Foundation Model for Analog Layout Design Automation

A Fast Design Optimization of On-Chip Equalizing Links Using Particle Swarm Optimization

An On-chip Low-Cost Averaging Digital Sampling Scope for 80-GS/s Measurement of Wireline Pulse Responses

3 x 16 Gb/s Compact Single-ended PAM4 Transmitters with Inverter-based Crosstalk Compensation for Memory Interfaces

A Layout-to-Generator Conversion Framework with Graphical User Interface for Visual Programming of Analog Layout Generators

A Single-Ended Inverter-based Addition-Only Feed-Forward Equalization Transmitter

Compact Single-ended Transceivers Demonstrating Flexible Generation of 1/N-rate Receiver Front-ends for Short-Reach Links

A 20-Gb/s/Pin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip Links

A Speculative Divide-and-Conquer Optimization Method for Large Analog/Mixed-Signal Circuits: A High-Speed FFE SST Transmitter Example

A Reflection Self-Canceling Design Technique for Multidrop Memory Interfaces

A Compact Single-Ended Inverter-based Transceiver with Swing Improvement for Short-Reach Links

A DFE-Enhanced Phase-Difference Modulation Signaling for Multi-Drop Memory Interfaces

A 7.8 Gb/s 2.9 pJ/b Single-Ended Receiver With 20 tap DFE for Highly-Reflective Channels

A 7.8 Gb/s/pin, 1.96 pJ/b Transceiver with Phase-Difference-Modulation Signaling for highly-Reflective Interconnects

Review: A Speculative Divide-and-Conquer Optimization Method for Large Analog/Mixed-Signal Circuits

A Cost-efficient FPGA-based Embedded System for Biosensor Platform

A Fast Eye Size Evaluation Method for High Speed Signal

A Layout Generator of Latch, Flip-Flop, and Shift Register for High-Speed Links

A 50 Mb/s Full HBC TRX with Adaptive DFE and Variable-Interval 3x Oversampling CDR in 28nm CMOS Technology for A 75 cm Body Channel Moving at 0.75 Cycle/sec

A Study On Reliable High-Speed HBC Enhanced by ECC for Wearable Neural Interfaces

A 20-Gb/s/pin 0.0024-mm^2 Single-Ended DECS TRX with CDR-less Self-Slicing/Auto-Deserialization to Improve Tolerance on Duty Cycle Error and RX Supply Noise for DCC/CDR-less Short-Reach Memory Interfaces

A 20Gb/s/pin 1.18pJ/b 1149μm2 Single-Ended Inverter-based 4-tap Addition-Only Feed-Forward Equalization Transmitter with Improved Robustness to Coefficient Errors in 28nm CMOS

GUI-Enhanced Layout Generation of FFE SST TXs for Fast High-Speed Serial Link Design

Experimental Verification of a Simple, Intuitive, and Accurate Closed-Form Transfer Function Model for Diverse High-Speed Interconnects

A Rule-of-thumb Condition to Avoid Large HRS Current in ReRAM Crossbar Array Design

A 12-Gb/s AC-Coupled FFE TX With Adaptive Relaxed Impedance Matching Achieving Adaptation Range of 35-75Ω Z0 and 30-550Ω RRX

A 7.8Gb/s/pin 1.96pJ/b Compact Single-Ended TRX and CDR with Phase-Difference Modulation for Highly-Reflective Memory Interfaces

A 16.6-pJ/b 150-Mb/s Body Channel Communication Transceiver with Decision Feedback Equalization Improving > 200x Area Efficiency

A 10-GHz Multi-purpose Reconfigurable Built-in Self-Test Circuit for High-Speed Links

Coefficient Error Robust Feed Forward Equalizer

Circuits and Methods for DFE with Reduced Area and Power Consumption

SYSTEM FOR TRANSCEIVING DATA BASED ON CLOCK TRANSITION TIME

COMPUTING DEVICE AND METHOD FOR ASSIGNING GENERATOR TO SEMICONDUCTOR LAYOUT AND METHOD OF TRAINING NEURAL NETWORK

USER INTERFACE METHOD OF SEMICONDUCTOR DESIGN PROGRAM AND OPERATION DEVICE THEREFOR

반도체 레이아웃의 제너레이터 할당 방법, 할당 학습 방법 및 연산 장치

반도체 설계 프로그램의 사용자 인터페이스 방법 및 연산 장치

BEVIL LAB

교수님 소개

김병섭

연구실 소개

연구실 키워드

알럼나이가 간 회사

연구실 지원 방법

대우 조건

연도별 논문 인용수

저널 & 학회 논문 출판 수

연구실 논문 목록

A Self-Supervised Learning of a Foundation Model for Analog Layout Design Automa…

A Self-Supervised Learning of a Foundation Model for Analog Layout Design Automation

A Fast Design Optimization of On-Chip Equalizing Links Using Particle Swarm Opti…

연구실 보유 특허

대학별 입시끈

우리 연구실 모집

교수님 소개

김병섭

연구실 키워드

알럼나이가 간 회사

연구실 지원 방법

대우 조건

연도별 논문 인용수

저널 & 학회 논문 출판 수

연구실 논문 목록

A Self-Supervised Learning of a Foundation Model for Analog Layout Design Automa…

A Self-Supervised Learning of a Foundation Model for Analog Layout Design Automation

A Fast Design Optimization of On-Chip Equalizing Links Using Particle Swarm Opti…

연구실 보유 특허

최근 3년간 연구실적 높은 연구실

대학별 입시끈

우리 연구실 모집