Welcome to the research group website of Dr. Il-Min Yi (Assistant Professor) in School of EECS, Gwangju Institute of Science and Technology (GIST), Korea. The research of our group is focused on semiconductor circuit design for various applications including high-speed wireline communication and data converter circuits.

반도체 회로 설계, 고속 유선 통신 및 데이터 변환기 회로를 포함한 다양한 애플리케이션을 위한 회로 설계에 중점을 둡니다.

A 46GS/s 7-bit Time-Interleaved Time-Domain ADC with Synthesizable Unit ADCs in 16nm FinFET

A 56Gbps DAC/ADC-Based Multicarrier Transceiver with TX Polar DSP and RX MIMO-DSP for> 40dB Loss Channel

A 56Gbps ADC/DAC-Based Jitter-Robust Multicarrier Transceiver with RX MIMO-DSP for > 40dB Loss Channel

Comparisons of Metastability Impact in Time-Domain and Asynchronous SAR ADCs for Serial I/O Receivers

A 50-Gb/s Multicarrier Transmitter Using DAC-Based Polar Drivers in 22-nm FinFET

Energy-Efficient Optical Transceiver Circuits Enabled by 3D Heterogeneous Integration

A 42.7Gb/s Optical Receiver With Digital Clock and Data Recovery in 28nm CMOS

A 3D Integrated Energy-Efficient Transceiver Realized by Direct Bond Interconnect of Co-Designed 12 nm FinFET and Silicon Photonic Integrated Circuits

A 25-Gb/s 3-D Direct Bond Silicon Photonic Receiver in 12-nm FinFET

A 50Gb/s DAC-Based Multicarrier Polar Transmitter in 22nm FinFET

A Sub-500fJ/bit 3D Direct Bond Silicon Photonic Transceiver in 12nm FinFET

A 38-GS/s 7-bit Pipelined-SAR ADC With Speed-Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET

A 42.7Gb/s Optical Receiver with Digital CDR in 28nm CMOS

A Direct Bond Interconnect 3D Co-Integrated Silicon-Photonic Transceiver in 12nm FinFET With -20.3dBm OMA Sensitivity and 691fJ/bit

A Jitter-Robust 40 Gb/s ADC-Based Multicarrier Receiver Front-End With 4-GS/s Baseband Pipeline-SAR ADCs in 22-nm FinFET

A Jitter-Robust 40Gb/s ADC-Based Multicarrier Receiver Front End in 22nm FinFET

A 38GS/s 7b Time-Interleaved Pipelined-SAR ADC with Speed-Enhanced Bootstrapped Switch in 22nm FinFET

LLM: Realizing Low-Latency Memory by Exploiting Embedded Silicon Photonics for Irregular Workloads

A 4-GS/s 11.3-mW 7-bit Time-Based ADC With Folding Voltage-to-Time Converter and Pipelined TDC in 65-nm CMOS

A 15.1-mW 6-GS/s 6-bit Single-Channel Flash ADC With Selectively Activated 8x Time-Domain Latch Interpolation

An Ultrathin Conformable Vibration-Responsive Electronic Skin for Quantitative Vocal Recognition

A 15.1-mW 6-GS/s 6-bit Flash ADC with Selectively Activated 8x Time-Domain Interpolation

A Summer-Embedded Sense Amplifier for High-Speed Decision Feedback Equalizer

A time-based receiver with 2-tap decision feedback equalizer for single-ended mobile DRAM interface

A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8V 65nm CMOS

A Single-Ended Parallel Transceiver with Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface

A Low-EMI Four-Bit Four-Wire Single-Ended DRAM Interface by Using a Three-Level Balanced Coding Scheme

A 40 mV-Differential-Channel-Swing Transceiver using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer with a CML driver at 9 Gb/s

EMI Issues in Pseudo-Differential Signaling for SDRAM Interface

A 40-mV-Swing Single-Ended Transceiver for TSV with a Switched-Diode RX Termination

An 80 mV-Swing Single-Ended Duobinary Transceiver With a TIA RX Termination for the Point-to-Point DRAM Interface

수신 단 TIA 터미네이션 기법의 단일 신호선 듀오바이너리 송수신 단 회로

An on-chip TSV emulation using metal bar surrounded by metal ring to develop interface circuits

A Transmitter to Compensate for Crosstalk-Induced Jitter by Subtracting a Rectangular Crosstalk Waveform From Data Signal During the Data Transition Time in Coupled Microstrip Lines

SIGMA-SPICE: A Parallel Mode SPICE for Multi-core CPU

SIGMA-SPICE: A SPICE3-based mixed-mode and parallel Monte Carlo circuit simulator

An ultrathin conformable vibration-responsive electronic skin for quantitative vocal recognition

A 38-GS/s 7-bit pipelined-SAR ADC with speed-enhanced bootstrapped switch and output level shifting technique in 22-nm FinFET

A 4-GS/s 11.3-mW 7-bit time-based ADC with folding voltage-to-time converter and pipelined TDC in 65-nm CMOS

An 80 mV-swing single-ended duobinary transceiver with a TIA RX termination for the point-to-point DRAM interface

A 3D integrated energy-efficient transceiver realized by direct bond interconnect of co-designed 12 nm FinFET and silicon photonic integrated circuits

A jitter-robust 40 Gb/s ADC-based multicarrier receiver front-end with 4-GS/s baseband pipeline-SAR ADCs in 22-nm FinFET

A 15.1-mW 6-GS/s 6-bit single-channel flash ADC with selectively activated 8× time-domain latch interpolation

A transmitter to compensate for crosstalk-induced jitter by subtracting a rectangular crosstalk waveform from data signal during the data transition time in coupled microstrip …

A 38GS/s 7b time-interleaved pipelined-SAR ADC with speed-enhanced bootstrapped switch in 22nm FinFET

A Single-Ended Parallel Transceiver With Four-Bit Four-Wire Four-Level Balanced Coding for the Point-to-Point DRAM Interface

A 40 mV-Differential-Channel-Swing Transceiver Using a RX Current-Integrating TIA and a TX Pre-Emphasis Equalizer With a CML Driver at 9 Gb/s

A 40-mV-swing single-ended transceiver for TSV with a switched-diode RX termination

23.7 A time-based receiver with 2-tap DFE for a 12Gb/s/pin single-ended transceiver of mobile DRAM interface in 0.8 V 65nm CMOS

A jitter-robust 40Gb/s ADC-based multicarrier receiver front end in 22nm FinFET

A 15.1-mW 6-GS/s 6-bit flash ADC with selectively activated 8× time-domain interpolation

A direct bond interconnect 3D Co-integrated silicon-photonic transceiver in 12nm FinFET with-20.3 dBm OMA sensitivity and 691fJ/bit

Decision feedback equalizer

LLM: Realizing low-latency memory by exploiting embedded silicon photonics for irregular workloads

Il-Min Yi

Assistant Professor

IC Design Lab

교수님 소개

이일민

연구실 소개

연구실 키워드

알럼나이가 간 회사

연구실 지원 방법

대우 조건

연도별 논문 인용수

저널 & 학회 논문 출판 수

연구실 논문 목록

A 46GS/s 7-bit Time-Interleaved Time-Domain ADC with Synthesizable Unit ADCs in 16nm FinFET

A 56Gbps DAC/ADC-Based Multicarrier Transceiver with TX Polar DSP and RX MIMO-DSP for> 40dB Loss Channel

A 56Gbps ADC/DAC-Based Jitter-Robust Multicarrier Transceiver with RX MIMO-DSP for > 40dB Loss Channel

연구실 보유 특허

대학별 입시끈

우리 연구실 모집

교수님 소개

이일민

연구실 키워드

알럼나이가 간 회사

연구실 지원 방법

대우 조건

연도별 논문 인용수

저널 & 학회 논문 출판 수

연구실 논문 목록

A 46GS/s 7-bit Time-Interleaved Time-Domain ADC with Synthesizable Unit ADCs in 16nm FinFET

A 56Gbps DAC/ADC-Based Multicarrier Transceiver with TX Polar DSP and RX MIMO-DSP for> 40dB Loss Channel

A 56Gbps ADC/DAC-Based Jitter-Robust Multicarrier Transceiver with RX MIMO-DSP for > 40dB Loss Channel

연구실 보유 특허

최근 3년간 연구실적 높은 연구실

대학별 입시끈

우리 연구실 모집