Namho Kwon

Jeik Choi

Banseok Shin

Seungpyo Lee

Gunil Kang

Hyunseob Shin

Sangwoo Jung

Sangwoo Hwang

Seock-Hwan Noh

Hojin Lee

Yejin Lee

Jiyong Park

Jahyun Koo

Intelligent digital systems lab
Welcome to IDSLab at KU!
Research topics
High-performance system design for training deep neural networks
Lightweight machine learning algorithms for energy-efficient inference engines
Automated search of efficient AI models
Energy-efficient hardware accelerator for scientific computing
Anti-tampering hardware using in-memory-computing
Spike-driven neural network design and its hardware implementation
Power-aware/thermal-aware system design methodology
Broader research interests include
efficient AI algorithms
,
digital IC design
, and
accelerator/computer architecture
. We look forward to working with highly motivated students.
Please send me an e-mail if you are interested in pursuing
a PhD or an integrated MS-PhD program.

지능형 디지털 시스템 연구실
KU IDSLab에 오신 것을 환영합니다!
연구 주제
심층 신경망 훈련을 위한 고성능 시스템 설계
에너지 효율적인 추론 엔진을 위한 경량 기계 학습 알고리즘
효율적인 AI 모델의 자동 검색
과학 컴퓨팅을 위한 에너지 효율적인 하드웨어 가속기
메모리 내 컴퓨팅을 사용하는 변조 방지 하드웨어
스파이크 구동 신경망 설계 및 하드웨어 구현
전력 인식/열 인식 시스템 설계 방법론
더 넓은 연구 관심사 포함
효율적인 AI 알고리즘
,
디지털 IC 설계
, 그리고
가속기/컴퓨터 아키텍처
. 의욕이 넘치는 학생들과 함께 일하기를 기대합니다.
박사 또는 통합 석박사 과정을 밟고 싶으시면 이메일을 보내주세요.

MX-SAFE: Versatile inference- and training-proof microscaling format with on-the-fly exponent and mantissa bit allocation

GustavSNN: Unleashing the power of Gustavson's algorithm on SNN acceleration with column-parallel tick-batch dataflow

Dissecting and Re-architecting 3D NAND Flash PIM Arrays for Efficient Single-Batch Token Generation in LLMs

CAM-CIM: A hybrid compute-in-memory using content-addressable memory with subword split mapping for reduced ADC resolution

RIMIX: RISC-V core with MIXed-precision SIMD instruction extensions supported by oracle-assisted sub-network search for efficient TinyML

Jack Unit: An area- and energy-efficient multiply-accumulate (MAC) unit supporting diverse data formats

FlexNeRFer: A multi-dataflow, adaptive sparsity-aware accelerator for on-device NeRF rendering

FlexENM: A flexible encrypting-near-memory with refresh-less eDRAM-based multi-mode AES

RISC-V driven orchestration of vector processing units and eFlash compute-in-memory arrays for fast and accurate keyword spotting

SpikedAttention: Training-free and fully spike-driven transformer-to-SNN conversion with winner-oriented spike shift for softmax operation

A 65nm 687.5-TOPS/W drive strength-based SRAM compute-in-memory macro with adaptive dynamic range for edge AI applications

OPAL: Outlier-preserved microscaling quantization accelerator for generative large language models

A ready-to-use RTL generator for systolic tensor arrays and analysis using open-source EDA tools

A 3.3-to-11V-supply-range 10μW/Ch arbitrary-waveform-capable neural stimulator with output-adaptive-self-bias and supply-tracking schemes in 0.18μm standard CMOS

NDPipe: exploiting near-data processing for scalable inference and continuous training in photo storage

A full SW-HW demonstration of GEMM accelerators with RISC-V instruction extensions

Fused-STA: Automated Design Space Exploration of a Fused Systolic Tensor Array for Universal Deep Learning Acceleration

A Hybrid Digital-Analog Compute-in-Memory Using Content-Addressable Memory with Flexible Multi-bit Slicing

All-rounder: A flexible AI accelerator with diverse data format support and morphable structure for multi-DNN processing

A Survey on Binary and Ternary Neural Networks and Their Realization in Compute-in-Memory

A dual-precision and low-power CNN inference engine using a heterogeneous processing-in-memory architecture

One-Spike SNN: single-spike phase coding with base manipulation for ANN-to-SNN conversion loss minimization

Skipformer: Evolving Beyond Blocks for Extensively Searching On-Device Language Models with Learnable Attention Window

Architectures for self-powered edge intelligence

Neurocube: A programmable digital neuromorphic architecture with high-density 3D memory

Design and analysis of approximate compressors for balanced error accumulation in MAC operator

Adaptive weight compression for memory-efficient neural networks

On-chip training of recurrent neural networks with limited numerical precision

Efficient object detection using embedded binarized neural networks

A power-aware digital multilayer perceptron accelerator with on-chip training based on approximate computing

A power-aware digital feedforward neural network platform with backpropagation driven approximate synapses

Simplified compressor and encoder designs for low-cost approximate radix-4 booth multiplier

Flexblock: A flexible dnn training accelerator with multi-mode block floating point support

Approximate LSTM computing for energy-efficient speech recognition

NeuroSensor: A 3D image sensor with integrated neural accelerator

Reram crossbar based recurrent neural network for human activity detection

On the Impact of Energy-Accuracy Tradeoff in a Digital Cellular Neural Network for Image Processing

Maximizing system performance by balancing computation loads in LSTM accelerators

One-spike snn: Single-spike phase coding with base manipulation for ann-to-snn conversion loss minimization

A Programmable Hardware Accelerator for Simulating Dynamical Systems

Thermal signature: A simple yet accurate thermal index for floorplan optimization

Dynamic approximation with feedback control for energy-efficient recurrent neural network hardware

A 1V 136.6 dB-DR 4kHz-BW Current-to-Digital Converter with a Truncation-Noise-Shaped Baseline-Servo-Loop in 0.18\mu\mathrm {m} $ CMOS

High-throughput near-memory processing on CNNs with 3D HBM-like memory

Saibal Mukhopadhyay

Duckhwan Kim

Youngjoo Lee

Sek Chai

Jong Hwan Ko

Jae-Joon Kim

Taesik Na

Yun Long

Youngsoo Shin

Sungjin Lee

Mohammad Faisal Amir

Daehoon Kim

Sachin Sapatnekar

Daehyun Ahn

Minki Cho

Marilyn Wolf

Burhan Ahmad Mudassar

Seungsik Moon

Seungwhun Paik

Jaeha Kung

This paper presents a programmable and scalable digital neuromorphic architecture based on 3D high-density memory integrated with logic tier for efficient neural computing. The proposed architecture consists of clusters of processing engines, connected by 2D mesh network as a processing tier, which is integrated in 3D with multiple tiers of DRAM. The PE clusters access multiple memory channels (vaults) in parallel. The operating principle, referred to as the memory centric computing, embeds specialized state-machines within the vault controllers of HMC to drive data into the PE clusters. The paper presents the basic architecture of the Neurocube and an analysis of the logic tier synthesized in 28nm and 15nm process technologies. The performance of the Neurocube is evaluated and illustrated through the mapping of a Convolutional Neural Network and estimating the subsequent power and performance for …

In this paper, we present a novel approximate computing scheme suitable for realizing the energy-efficient multiply-accumulate (MAC) processing. In contrast to the prior works that suffer from the error accumulation limiting the approximate range, we utilize different approximate multipliers in an interleaved way to compensate errors in the opposite direction during accumulate operations. For the balanced error accumulation, we first design the approximate 4-2 compressors generating errors in the opposite direction while minimizing the computational costs. Based on the probabilistic analysis, positive and negative multipliers are then carefully developed to provide a similar error distance. Simulation results on various practical applications reveal that the proposed MAC processing offers the energy-efficient computing scenario by extending the range of approximate parts. Even compared to the state-of-the-art …

Neural networks generally require significant memory capacity/bandwidth to store/access a large number of synaptic weights. This paper presents an application of JPEG image encoding to compress the weights by exploiting the spatial locality and smoothness of the weight matrix. To minimize the loss of accuracy due to JPEG encoding, we propose to adaptively control the quantization factor of the JPEG algorithm depending on the error-sensitivity (gradient) of each weight. With the adaptive compression technique, the weight blocks with higher sensitivity are compressed less for higher accuracy. The adaptive compression reduces memory requirement, which in turn results in higher performance and lower energy of neural network hardware. The simulation for inference hardware for multilayer perceptron with the MNIST dataset shows up to 42X compression with less than 1% loss of recognition accuracy …

Training of neural network can be accelerated by limited numerical precision together with specialized low-precision hardware. This paper studies how low precision can impact on entire training of RNNs. We emulate low precision training for recently proposed gated recurrent unit (GRU) and use dynamic fixed point as a target numeric format. We first show that batch normalization on input sequences can help speed up training with low precision as well as high precision. We also show that the overflow rate should be carefully controlled for dynamic fixed point. We study low precision training with various rounding options including bit truncation, round to nearest, and stochastic rounding. Stochastic rounding shows superior results than the other options. The effect of fully low precision training is also analyzed by comparing partial low precision training. We show that the piecewise linear activation function with …

Memory performance is a key bottleneck for deep learning systems. Binarization of both activations and weights is one promising approach that can best scale to realize the highest energy efficient system using the lowest possible precision. In this paper, we utilize and analyze the binarized neural network in doing human detection on infrared images. Our results show comparable algorithmic performance of binarized versus 32bit floating-point networks, with the added benefit of greatly simplified computation and reduced memory overhead. In addition, we present a system architecture designed specifically for computation using binary representation that achieves at least 4× speedup and the energy is improved by three orders of magnitude over GPU.

This paper proposes that approximation by reducing bit-precision and using inexact multiplier can save power consumption of digital multilayer perceptron accelerator during the classification of MNIST (inference) with negligible accuracy degradation. Based on the error sensitivity precomputed during the training, synaptic weights with less sensitivity are approximated. Under given bit-precision modes, our proposed algorithm determines bit precision for all synapse to minimize power consumption for given target accuracy. For entire network, earlier layer can be more approximated since it has lower error sensitivity. Proposed algorithm can save power 57.4 percent while accuracy is degraded about 1.7 percent. After approximation, retraining with few iterations can improve the accuracy while maintaining power consumption. The impact of different training conditions on the approximation is also studied. Training with …

This paper proposes a power-aware digital feedforward neural network platform that utilizes the backpropagation algorithm during training to enable energy-quality trade-off. Given a quality constraint, the proposed approach identifies a set of synaptic weights for approximation in a neural network. The approach selects synapses with small impact on output error, estimated by the backpropagation algorithm, for approximation. The approximations are achieved by a coupled software (reduced bit-width) and hardware (approximate multiplication in the processing engine) based design approaches. The full-chip design in 130nm CMOS shows, compared to a baseline accurate design, the proposed approach reduces system power by ~38% with 0.4% lower recognition accuracy in a classification problem.

In this brief, we present a novel design methodology of cost-effective approximate radix-4 Booth multipliers, which can significantly reduce the power consumption of error-resilient signal processing tasks. In contrast that the prior studies only focus on the approximation of either the partial product generation with encoders or the partial product reductions with compressors, the proposed method considers two major processing steps jointly by forcing the generated error directions to be opposite to each other. As the internal errors are naturally balanced to have zero mean, as a result, the proposed approximate Booth multiplier can minimize the required processing energy under the same number of approximate bits compared to the previous designs. Simulation results on FIR filtering and image classification applications reveal that the proposed approximate Booth multiplier shows the most attractive energy …

When training deep neural networks (DNNs), expensive floating point arithmetic units are used in GPUs or custom neural processing units (NPUs). To reduce the burden of floating point arithmetic, community has started exploring the use of more efficient data representations, e.g., block floating point (BFP). The BFP format allows a group of values to share an exponent, which effectively reduces the memory footprint and enables cheaper fixed point arithmetic for multiply-accumulate (MAC) operations. However, existing BFP-based DNN accelerators are targeted for a specific precision, making them less versatile. In this paper, we present FlexBlock, a DNN training accelerator with three BFP modes, possibly different among activation, weight, and gradient tensors. By configuring FlexBlock to a lower BFP precision, the number of MACs handled by the core increases by up to 4× in 8-bit mode or 16× in 4-bit mode compared to …

This paper presents an approximate computing method of long short-term memory (LSTM) operations for energy-efficient end-to-end speech recognition. We newly introduce the concept of similarity score, which can measure how much the inputs of two adjacent LSTM cells are similar to each other. Then, we disable the highly-similar LSTM operations and directly transfer the prior results for reducing the computational costs of speech recognition. The pseudo-LSTM operation is additionally defined for providing the approximate computation with reduced processing resolution, which can further relax the processing overheads without degrading the accuracy. In order to verify the proposed idea, in addition, we design an approximate LSTM accelerator in 65 nm CMOS process. The proposed accelerator newly utilizes a number of approximate processing elements (PEs) to support the proposed skipped-LSTM and pseudo-LSTM operations without degrading the energy efficiency. Moreover, sparsity-aware scheduling is introduced by introducing the small-sized on-chip SRAM buffer. As a result, the proposed work provides an energy-efficient but still accurate speech recognition system, which consumes 2.19 times less energy than the baseline architecture.

3D integration provides opportunities to design high-bandwidth and low-power CMOS image sensors (CIS) [1-4]. The 3D stacking of pixel tier, peripheral tier, memory tier(s), and compute tier(s) enables high degree of parallel processing. Also, each tier can be designed in different technology nodes (heterogeneous integration) to further improve power-efficiency. This paper presents a case study of a smart 3D image sensor with integrated neuro-inspired computing for intelligent vision processing. Hardware acceleration of neuro-inspired computing has received much attention in recent years for recognition and classification [5]. We present the physical design of NeuroSensor, a 3D CIS with an integrated convolutional neural network (CNN) accelerator. The rationale for our approach is that 3D integration of sensor, memory, and computing will effectively harness the inherent parallelism in neural algorithms. We …

We present a programmable high-efficient Recurrent Neural Network (RNN) with Synapses design using Resistive Random Access Memory (ReRAM). The presented ReRAM-RNN employs crossbar ReRAM arrays as synapses. A fast synapses programming methodology is realized by CMOS-based neuron with in-built programming circuitry. The simulations are performed using experimentally verified physical resistive switching model, instead of only functional models, providing better estimate of system speed and power efficiency. Simulation results show that ReRAM-RNN can provide higher computation efficiency and/or more compact design than software realization of RNN, and dedicated CMOS based digital-and analog-RNN. We show that the efficiency improvement of ReRAM-based neural network design is more significant in feedback networks than in feedforward networks.

This paper studies the opportunities of energy-accuracy tradeoff in cellular neural network (CNN). Algorithmic characteristics of CNN is coupled with hardware-induced error distribution of a digital CNN cell to evaluate energy-accuracy tradeoff for simple image processing tasks as well as a complex application. The analysis shows that errors modulate the cell dynamics and propagate through the network degrading the output quality and increasing the convergence time. The error propagation is determined by the task being performed by the CNN, specifically, the strength of the feedback template. Controlling precision is observed to be a more effective approach for energy-accuracy tradeoff in CNN than voltage over scaling.

The LSTM is a popular neural network model for modeling or analyzing the time-varying data. The main operation of LSTM is a matrix-vector multiplication and it becomes sparse (spMxV) due to the widely-accepted weight pruning in deep learning. This paper presents a new sparse matrix format, named CBSR, to maximize the inference speed of the LSTM accelerator. In the CBSR format, speed-up is achieved by balancing out the computation loads over PEs. Along with the new format, we present a simple network transformation to completely remove the hardware overhead incurred when using the CBSR format. Also, the detailed analysis on the impact of network size or the number of PEs is performed, which lacks in the prior work. The simulation results show 16~38% improvement in the system performance compared to the well-known CSC/CSR format. The power analysis is also performed in 65nm CMOS …

As spiking neural networks (SNNs) are event-driven, energy efficiency is higher than conventional artificial neural networks (ANNs). Since SNN delivers data through discrete spikes, it is difficult to use gradient methods for training, limiting its accuracy. To keep the accuracy of SNNs similar to ANN counterparts, pre-trained ANNs are converted to SNNs (ANN-to-SNN conversion). During the conversion, encoding activations of ANNs to a set of spikes in SNNs is crucial for minimizing the conversion loss. In this work, we propose a single-spike phase coding as an encoding scheme that minimizes the number of spikes to transfer data between SNN layers. To minimize the encoding error due to single-spike approximation in phase coding, threshold shift and base manipulation are proposed. Without any additional retraining or architectural constraints on ANNs, the proposed conversion method does not lose inference …

The fast and energy-efficient simulation of dynamical systems defined by coupled ordinary/partial differential equations has emerged as an important problem. The accelerated simulation of coupled ODE/PDE is critical for analysis of physical systems as well as computing with dynamical systems. This paper presents a fast and programmable accelerator for simulating dynamical systems. The computing model of the proposed platform is based on multilayer cellular nonlinear network (CeNN) augmented with nonlinear function evaluation engines. The platform can be programmed to accelerate wide classes of ODEs/PDEs by modulating the connectivity within the multilayer CeNN engine. An innovative hardware architecture including data reuse, memory hierarchy, and near-memory processing is designed to accelerate the augmented multilayer CeNN. A dataflow model is presented which is supported by optimized …

A floorplanning has a potential to reduce chip temperature due to the conductive nature of heat. If floorplan optimization, which is usually based on simulated annealing, is employed to reduce temperature, its evaluation should be done extremely fast with high accuracy. A new thermal index, named thermal signature, is proposed. It approximates the temperature calculation, which is done by taking the product of Green's function and power density integrated over space. The correlation coefficient between thermal signature and temperature is shown to be quite high, more than 0.7 in many examples. A floorplanner that uses thermal signature is constructed and assessed using real design examples in 32-nm technology. It produces a floorplan whose maximum temperature is 11.4°C smaller than that of standard floorplan, on average, in reasonable amount of runtime.

This paper presents methodology of feedback-controlled dynamic approximation to enable energy-accuracy trade-off in digital recurrent neural network (RNN). A low-power digital RNN engine is presented that employs the proposed dynamic approximation. The on-chip feedback controller is realized by utilizing hysteretic or proportional controller. The dynamic adaptation of bit-precisions during the RNN computation is selected as approximation approach. Considering various applications, the digital RNN engine designed in 28nm CMOS shows ~36% average energy saving compared to the baseline case, with only ~4% of accuracy degradation on average.

Precise current measurements underpin emerging applications such as photoplethysmography (PPG), electrochemical sensing, and fast-scan cyclic voltammetry (FSCV) [1–6], where the signal is a low-swing current that rides on a large, slow-varying baseline. Therefore, readout systems need a dynamic-range (DR) > 120dB, bandwidth (BW) >1 kHz, noise floor , and power <1 mW (Fig. 32.3.1 left). To widen DR, prior front-ends employ a prediction DAC [1], threshold-filter-based feedback-loop [2], and a Reset-Then-Open (RTO) DAC [3]. However, they widen the DR by sacrificing BW or power (Fig. 32.3.1 right). For instance, [1] employing a prediction DAC requires a power-hungry digital backend, while [2] with a threshold-filter-based feedback-loop is BW-limited (~20Hz). In contrast, [3] achieves wide-DR and BW, but consumes> 1 mW power. This paper presents a continuous-tirne current-to-digital …

This article discusses the high-performance near-memory neural network (NN) accelerator architecture utilizing the logic die in three-dimensional (3D) High Bandwidth Memory– (HBM) like memory. As most of the previously reported 3D memory-based near-memory NN accelerator designs used the Hybrid Memory Cube (HMC) memory, we first focus on identifying the key differences between HBM and HMC in terms of near-memory NN accelerator design. One of the major differences between the two 3D memories is that HBM has the centralized through- silicon-via (TSV) channels while HMC has distributed TSV channels for separate vaults. Based on the observation, we introduce the Round-Robin Data Fetching and Groupwise Broadcast schemes to exploit the centralized TSV channels for improvement of the data feeding rate for the processing elements. Using synthesized designs in a 28-nm CMOS technology …

IDSLab

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MX-SAFE: Versatile inference- and training-proof microscaling format with on-the-fly exponent and mantissa bit allocation

GustavSNN: Unleashing the power of Gustavson's algorithm on SNN acceleration with column-parallel tick-batch dataflow

A Hybrid Digital-Analog Compute-in-Memory Using Content-Addressable Memory with Flexible Multi-bit Slicing

연구실 보유 특허

대학별 입시끈

우리 연구실 모집

교수님 소개

궁재하

연구실 키워드

알럼나이가 간 회사

연구실 지원 방법

대우 조건

연도별 논문 인용수

저널 & 학회 논문 출판 수

연구실 논문 목록

MX-SAFE: Versatile inference- and training-proof microscaling format with on-the-fly exponent and mantissa bit allocation

GustavSNN: Unleashing the power of Gustavson's algorithm on SNN acceleration with column-parallel tick-batch dataflow

A Hybrid Digital-Analog Compute-in-Memory Using Content-Addressable Memory with Flexible Multi-bit Slicing

연구실 보유 특허

최근 3년간 연구실적 높은 연구실

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