Geonwoo Choi

Hunjong Lee

Jaewon Seo

Jiwon Shin

Dowon Kwon

Yewon Hwang

Hyunwoo Moon

Inje Kim

Boyoung Park

Jongmin Lee

Seungho Jung

The Computer System Architecture Lab at Korea University focuses on computer architecture and systems research. The lab encourages prospective Master's and Ph.D. students to participate in the intern program. Interested individuals should contact Prof. Gunjae Koo for more information regarding intern positions or open positions for self-motivated students.

고려대학교 컴퓨터 시스템 구조 연구실은 컴퓨터 구조 및 시스템 연구에 중점을 둔다. 석사 및 박사 과정에 관심 있는 학생들에게 인턴 프로그램 참여를 권장하며, 관심 있는 학생은 Gunjae Koo 교수에게 문의할 수 있다.

MOST: Memory Oversubscription-Aware Scheduling for Tensor Migration on GPU Unified Storage

SSFFT: Energy-Efficient Selective Scaling for Fast Fourier Transform in Embedded GPUs

SparsePIM: An Efficient HBM-Based PIM Architecture for Sparse Matrix-Vector Multiplications

Hierarchical Traversal Stack Design Using Shared Memory for GPU Ray Tracing

HyMM: A Hybrid Sparse-Dense Matrix Multiplication Accelerator for GCNs

Beyond VABlock: Improving Transformer Workloads through Aggressive Prefetching

Coldmap: Extending SSD Lifetime Exploiting Multi-Page Mapping Information

VitBit: Enhancing Embedded GPU Performance for AI Workloads through Register Operand Packing

Performance Analysis of GEMV Kernels by GPU and PIM Memory Address Mapping Approaches

Cache Side-Channel Attacks Exploiting RoCC Interface on RISC-V SoC Platform

SAVector: Vectored Systolic Arrays

Conflict-Aware Compiler for Hierarchical Register File on GPUs

Adaptive Kernel Merge and Fusion for Multi-Tenant Inference in Embedded GPUs

Warped-MC: An Efficient Memory Controller Scheme for Massively Parallel Processors

Performance Analysis of Embedding Cache Models for Optimizing Data Movement in Recommendation Systems

Vizard: Passing over Profiling-Based Detection by Manipulating Performance Counters

Performance Analysis of the Modern Genome Alignment Application

Analyzing GCN Aggregation on GPU

GhostLeg: Selective Memory Coalescing for Secure GPU Architecture

Performance Analysis of Graph Convolutional Networks on Accelerator Architectures

Stealth ECC: A Data-Width Aware Adaptive ECC Scheme for DRAM Error Resilience

CacheRewinder: Revoking Speculative Cache Updates Exploiting Write-Back Buffer

FLIXR: Embedding Index into Flash Translation Layer in SSDs

Restore Buffer Overflow Attacks: Breaking Undo-Based Defense Schemes

Analyzing the Performance of GCN Inferences with respect to Sparsity of Graph Features

Analyzing Data Cache Performance of Modern GPU Architecture

Analyzing Characteristics of Memory Timing Side-Channels in GPU

Processor and Operation Thereof to Revoke Cache Memory States Utilizing Write-Back Buffer

RT-Sniper: A Low-Overhead Defense Mechanism Pinpointing Cache Side-Channel Attacks

Revealing Characteristics of GCN Inference Models Using a GPU Profiler

Dynamic Near-Data Processing Control Mechanism Based on Computer Resource Availability on Solid-State Disk Platforms

Audio Compression Accelerator Design for Improving the Response Time of AI Speakers

Hi-End: Hierarchical, Endurance-Aware STT-MRAM-Based Register File for Energy-Efficient GPUs

Linebacker: Preserving Victim Cache Lines in Idle Register Files of GPUs

GraphSSD: Graph Semantics Aware SSD

Increasing Read Pending Queue Capacity to Increase Memory Bandwidth

CTA-Aware Prefetching and Scheduling for GPU

Summarizer: Trading Communication with Computing near Storage

Access Pattern-Aware Cache Management for Improving Data Utilization in GPU

Improving Energy Efficiency of GPUs through Data Compression and Compressed Execution

Warped-Preexecution: A GPU Pre-Execution Approach for Improving Latency Hiding

Revealing Critical Loads and Hidden Data Locality in GPGPU Applications

Warped-Compression: Enabling Power Efficient GPUs through Register Compression

Complementary Block-Based Motion Estimation for Frame Rate Up-Conversion

A Robust PRML Read Channel with Digital Timing Recovery for Multi-Format Optical Disc

Summarizer: trading communication with computing near storage

Warped-compression: Enabling power efficient gpus through register compression

GraphSSD: graph semantics aware SSD

Access pattern-aware cache management for improving data utilization in GPU

Warped-preexecution: A GPU pre-execution approach for improving latency hiding

Cta-aware prefetching and scheduling for gpu

Improving energy efficiency of gpus through data compression and compressed execution

Revealing critical loads and hidden data locality in GPGPU applications

Linebacker: Preserving victim cache lines in idle register files of GPUs

CTA-aware Prefetching for GPGPU

Hi-End: Hierarchical, endurance-aware STT-MRAM-based register file for energy-efficient GPUs

Stealth ECC: A data-width aware adaptive ECC scheme for DRAM error resilience

T. I, HKG Narra, J. Li, H

Savector: Vectored systolic arrays

Frequency detection method for optical disc bit data reproduction apparatus

Analyzing GCN aggregation on GPU

Dynamic near-data processing control mechanism based on computer resource availability on solid-state disk platforms

FLIXR: Embedding index into flash translation layer in SSDs

Increasing read pending queue capacity to increase memory bandwidth

Cacherewinder: revoking speculative cache updates exploiting write-back buffer

Murali Annavaram

Yunho Oh

Myung Kuk Yoon

Won Woo Ro

Hyeran Jeon

Hung-Wei Tseng

Keunsoo Kim

Te I

Steven Swanson

Krishna Giri Narra

Taeweon Suh

Sangun Choi

Haipeng Zha

Nam Sung Kim

Zhenhong Liu

Gunjae Koo

Modern data center solid state drives (SSDs) integrate multiple general-purpose embedded cores to manage flash translation layer, garbage collection, wear-leveling, and etc., to improve the performance and the reliability of SSDs. As the performance of these cores steadily improves there are opportunities to repurpose these cores to perform application driven computations on stored data, with the aim of reducing the communication between the host processor and the SSD. Reducing host-SSD bandwidth demand cuts down the I/O time which is a bottleneck for many applications operating on large data sets. However, the embedded core performance is still significantly lower than the host processor, as generally wimpy embedded cores are used within SSD for cost effective reasons. So there is a trade-off between the computation overhead associated with near SSD processing and the reduction in …

This paper presents Warped-Compression, a warp-level register compression scheme for reducing GPU power consumption. This work is motivated by the observation that the register values of threads within the same warp are similar, namely the arithmetic differences between two successive thread registers is small. Removing data redundancy of register values through register compression reduces the effective register width, thereby enabling power reduction opportunities. GPU register files are huge as they are necessary to keep concurrent execution contexts and to enable fast context switching. As a result register file consumes a large fraction of the total GPU chip power. GPU design trends show that the register file size will continue to increase to enable even more thread level parallelism. To reduce register file data redundancy warped-compression uses low-cost and implementation-efficient base-delta …

Graph analytics play a key role in a number of applications such as social networks, drug discovery, and recommendation systems. Given the large size of graphs that may exceed the capacity of the main memory, application performance is bounded by storage access time. Out-of-core graph processing frameworks try to tackle this storage access bottleneck through techniques such as graph sharding, and sub-graph partitioning. Even with these techniques, the need to access data across different graph shards or sub-graphs causes storage systems to become a significant performance hurdle. In this paper, we propose a graph semantic aware solid state drive (SSD) framework, called GraphSSD, which is a full system solution for storing, accessing, and performing graph analytics on SSDs. Rather than treating storage as a collection of blocks, GraphSSD considers graph structure while deciding on graph layout …

Long latency of memory operation is a prominent performance bottleneck in graphics processing units (GPUs). The small data cache that must be shared across dozens of warps (a collection of threads) creates significant cache contention and premature data eviction. Prior works have recognized this problem and proposed warp throttling which reduces the number of active warps contending for cache space. In this paper we discover that individual load instructions in a warp exhibit four different types of data locality behavior: (1) data brought by a warp load instruction is used only once, which is classified as streaming data (2) data brought by a warp load is reused multiple times within the same warp, called intra-warp locality (3) data brought by a warp is reused multiple times but across different warps, called inter-warp locality (4) and some data exhibit both a mix of intra- and inter-warp locality. Furthermore, each …

This paper presents a pre-execution approach for improving GPU performance, called P-mode (pre-execution mode). GPUs utilize a number of concurrent threads for hiding processing delay of operations. However, certain long-latency operations such as off-chip memory accesses often take hundreds of cycles and hence leads to stalls even in the presence of thread concurrency and fast thread switching capability. It is unclear if adding more threads can improve latency tolerance due to increased memory contention. Further, adding more threads increases on-chip storage demands. Instead we propose that when a warp is stalled on a long-latency operation it enters P-mode. In P-mode, a warp continues to fetch and decode successive instructions to identify any independent instruction that is not on the long latency dependence chain. These independent instructions are then pre-executed. To tackle write-after …

Albeit GPUs are supposed to be tolerant to long latency of data fetch operation, we observe that L1 cache misses occur in a bursty manner for many memory-intensive applications. This in turn leads to severe contentions in GPU memory hierarchy, and thus stalls execution pipeline for many cycles as all warps end up waiting for their memory requests to be serviced by L1 cache. To spread such bursty L1 cache misses, we propose CTA-Aware Prefetcher and Scheduler (CAPS) consisting of a thread group-aware prefetcher and a prefetch-aware warp scheduler for GPUs. GPU kernels group threads into cooperative thread arrays (CTAs). Each thread typically uses its thread index and its associated CTA index to identify the data that it operates on. The starting base address accessed by the first warp in a CTA is difficult to predict since that starting address is a complex function of thread index and CTA index and also …

GPU design trends show that the register file size will continue to increase to enable even more thread level parallelism. As a result register file consumes a large fraction of the total GPU chip power. This paper explores register file data compression for GPUs to improve power efficiency. Compression reduces the width of the register file read and write operations, which in turn reduces dynamic power. This work is motivated by the observation that the register values of threads within the same warp are similar, namely the arithmetic differences between two successive thread registers is small. Compression exploits the value similarity by removing data redundancy of register values. Without decompressing operand values some instructions can be processed inside register file, which enables to further save energy by minimizing data movement and processing in power hungry main execution unit. Evaluation results …

In graphics processing units (GPUs), memory access latency is one of the most critical performance hurdles. Several warp schedulers and memory prefetching algorithms have been proposed to avoid the long memory access latency. Prior application characterization studies shed light on the interaction between applications, GPU micro architecture and memory subsystem behavior. Most of these studies, however, only present aggregate statistics on how memory system behaves over the entire application run. In particular, they do not consider how individual load instructions in a program contribute to the aggregate memory system behavior. The analysis presented in this paper shows that there are two distinct classes of load instructions, categorized as deterministic and non-deterministic loads. Using a combination of profiling data from a real GPU card and cycle accurate simulation data we show that there is a …

Modern GPUs suffer from cache contention due to the limited cache size that is shared across tens of concurrently running warps. To increase the per-warp cache size prior techniques proposed warp throttling which limits the number of active warps. Warp throttling leaves several registers to be dynamically unused whenever a warp is throttled. Given the stringent cache size limitation in GPUs this work proposes a new cache management technique named Linebacker (LB) that improves GPU performance by utilizing idle register file space as victim cache space. Whenever a CTA becomes inactive, linebacker backs up the registers of the throttled CTA to the off-chip memory. Then, linebacker utilizes the corresponding register file space as victim cache space. If any load instruction finds data in the victim cache line, the data is directly copied to the destination register through a simple register-register move operation …

In this paper, we propose a thread group-aware stride prefetching scheme for GPUs. GPU kernels group threads into cooperative thread arrays (CTAs). Each thread typically uses its thread index and its associated CTA index to identify the data that it operates on. The starting base address accessed by the first warp in a CTA is difficult to predict, since that starting address is a complex function of thread index and CTA index and also depends on how the programmer distributes input data across CTAs. But threads within each CTA exhibit stride accesses. Hence, if the base address of each CTA can be computed early, it is possible to accurately predict prefetch addresses for threads within a CTA. To compute the base address of each CTA, a leading warp is used from each CTA. The leading warp is executed early by pairing it with warps from currently executing leading CTA. The warps in the leading CTA are used to compute the stride value. The stride value is then combined with base addresses computed from the leading warp of each CTA to prefetch the data for all the trailing warps in the trailing CTAs. Through simple enhancements to the existing two-level scheduler, prefetches can be issued sufficiently ahead of time before the demand requests. CTA-aware prefetch predicts addresses with over 99.27% accuracy and is able to improve GPU performance by 10%.

Modern Graphics Processing Units (GPUs) require large hardware resources for massive parallel thread executions. In particular, modern GPUs have a large register file composed of Static Random Access Memory (SRAM). Due to the high leakage current of SRAM, the register file consumes approximately 20% of the total GPU energy. The energy efficiency of the register file becomes more critical as the throughput of GPUs increases. For more energy-efficient GPUs, the usage of non-volatile memory such as Spin-Transfer Torque Magnetic Random Access Memory (STT-MRAM) as the GPU register file has been studied extensively. STT-MRAM requires a lower leakage current compared to SRAM and provides an appropriate read performance. However, using STT-MRAM directly in the GPU register file causes problems in performance and endurance because of complicated write procedures and material …

As DRAM process technology scales down and DRAM density continues to grow, DRAM errors have become a primary concern in modern data centers. Typically, data centers have adopted memory systems with a single error correction double error detection (SECDED) code. However, the SECDED code is not sufficient to satisfy DRAM reliability demands as memory systems get more vulnerable. Though the servers in data centers employ strong ECC schemes, such ECC schemes lead to substantial performance and/or storage overhead. In this paper, we propose Stealth ECC, a cost-effective memory protection scheme providing stronger error correctability than the conventional SECDED code, with negligible performance overhead and without storage overhead. Depending on the data-width (either narrow-width or full-width), Stealth ECC adaptively selects ECC schemes. For narrow-width values, Stealth ECC …

Conventional DNN inference accelerators are designed with a few (up to four) large systolic arrays. As such a scale-up architecture often suffers from low utilization, a scale-out architecture, in which a single accelerator has tens of pods and each pod has a small systolic array, has been proposed. While the scale-out architecture is promising, it still incurs increasing off-chip memory access as the pods are supposed to access the duplicate tiles of tensors. Prior work has proposed a shared buffer structure to address the problem, but those architectures suffer from performance degradation due to shared buffer access latency. We make an observation that all the pods access the same rows of input and weights within a short time window. With the observation, we propose a new inference accelerator architecture, called Vectored Systolic Arrays (SAVector). SAVector consists of a new two-level on-chip buffer …

The present invention relates to a frequency detection method for an optical disc bit data reproduction apparatus. The fre quency detection method uses the optical disc bit data repro duction apparatus including an Analog to Digital Converter (ADC), an interpolator, an asymmetry compensator, a digital bit and Successive bit length detector, a frequency detector, a phase detector and a Digital Controlled Oscillator (DCO). In the frequency detection method includes the primary fre quency detection step and the secondary frequency detection step. In the primary frequency detection step, status of input RF digital bit data frequency versus sampling frequency is determined and the sampling frequency is corrected so as to allow the sampling frequency to be rapidly adjusted to the frequency of the RF digital bit data, thus primarily detecting frequency. In the secondary frequency detection step, the sampling frequency is …

Graph convolutional neural networks (GCNs) are emerging neural networks for graph structures that include large features associated with each vertex. The operations of GCN can be divided into two phases - aggregation and combination. While the combination just performs matrix multiplications using trained weights and aggregated features, the aggregation phase requires graph traversal to collect features from adjacent vertices. Even though neural network applications rely on GPU’s massively parallel processing, GCN aggregation kernels exhibit rather low performance since graph processing using compressed graph structures provokes frequent irregular accesses in GPUs. In order to investigate the performance hurdles of GCN aggregation on GPU, we perform an in-depth analysis of the aggregation kernels using real GPU hardware and a cycle-accurate GPU simulator. We first analyze the characteristics …

(72) Inventors: Murali Annavaram, Los Angeles, CA (US); Gunjae Koo, Los Angeles, CA (U); Kran Kumar M? m, Angeles, CA (US); Hung-Wei Tseng, Los Angeles, CA (US)(21) Appl. No.: 16/650,758 (22) PCT Filed: Oct. 9, 2018 (86) PCT No.: PCT/US2018/055072 $3711 Date: Mar. 25, 2020 Related US Application at (60) Provisional application No. 62/570,554, filed on Oct. 10, 2017 Methods, systems, and apparatus for near-store computing. The summarizer system includes a task controller. The task controller is configured to receive, from a host, a work item. The task controller is configured to determine a current workload of a storage controller on a solid state drive (SSD). The task controller is configured to determine a work strategy to utilize at least one of the host or the storage controller based on the current workload of the storage

Flash memory technologies rely on flash translation layer (FTL) to manage no in-place update and garbage collection. Current FTL management schemes do not exploit the semantics of the accessed data. In this paper, we explore how semantic knowledge can be exploited to build and maintain indexes for stored data automatically. Data indexing is a critical enabler to accelerate many database applications and big data analytics. Unlike traditional per-table or per-file indexes that are managed separately from the data, we propose to maintain indexes on a per-flash page basis. Our approach, called FLash IndeXeR (FLIXR), builds and maintains page-level indexes whenever a page is written into the flash. FLIXR updates the indexes alongside any data updates at page granularity. The cost of the index update is hidden in the page write delays. FLIXR stores index data for each page within the FTL entry associated …

Inventors: Gunjae Koo, Claremont, CA (US); Vivek Kozhikkottu, Hillsboro, OR (US); Shankar Ganesh Ramasubramanian, Hillsboro, OR (US); Christopher B. Wilkerson, Portland, OR (US)

Transient execution attacks are critical security threats since those attacks exploit speculative execution which is an essential architectural solution that can improve the performance of out-of-order processors significantly. Such attacks change cache state by accessing secret data during speculative executions, then the attackers leak the secret information exploiting cache timing side-channels. Even though software patches against transient execution attacks have been proposed, the software solutions significantly slow down the performance of a system. In this paper, we propose CacheRewinder, an efficient hardware-based defense mechanism against transient execution attacks. CacheRewinder prevents leakage of secret information by revoking the cache updates done by speculative executions. To restore the cache state efficiently, CacheRewinder exploits the underutilized write-back buffer space as the …

Computer System Architecture Lab

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MOST: Memory Oversubscription-Aware Scheduling for Tensor Migration on GPU Unified Storage

SSFFT: Energy-Efficient Selective Scaling for Fast Fourier Transform in Embedded GPUs

SparsePIM: An Efficient HBM-Based PIM Architecture for Sparse Matrix-Vector Multiplications

연구실 보유 특허

대학별 입시끈

우리 연구실 모집

교수님 소개

구건재

연구실 키워드

알럼나이가 간 회사

연구실 지원 방법

대우 조건

연도별 논문 인용수

저널 & 학회 논문 출판 수

연구실 논문 목록

MOST: Memory Oversubscription-Aware Scheduling for Tensor Migration on GPU Unified Storage

SSFFT: Energy-Efficient Selective Scaling for Fast Fourier Transform in Embedded GPUs

SparsePIM: An Efficient HBM-Based PIM Architecture for Sparse Matrix-Vector Multiplications

연구실 보유 특허

최근 3년간 연구실적 높은 연구실

대학별 입시끈

우리 연구실 모집